Power metal-oxide-semiconductor field-effect transistors (mosfets) have been used for many years as active switch for various power converter topologies. Today, state-of-the-art silicon carbide (SiC) power mosfets are gradually replacing silicon (Si) insulated-gate bipolar transistors (IGBTs) in medium- to high-voltage and high-temperature power electronic applications [1]–[3]. Current–voltage (I–V) and capacitance-voltage (C–V) characteristics of power mosfets are important for evaluating their electrical performances, optimizing fabrication processes, improving device design, and calibrating compact device models [4]. Accurate device models are a valuable tool for predicting device switching dynamics, power losses, and electromagnetic interference noise generation in a computationally efficient and accurate way [5], [6]. Compact models based on the equivalent circuit shown in Fig. 1 have successfully been used for modeling both dynamic and static behavior of power mosfets [7]. A compact model describes the power mosfet’s macroscopic I–V characteristics, C–V characteristics, and thermal behavior. The output ($C_\text{oss}$), input ($C_\text{iss}$), and reverse transfer ($C_\text{rss}$) capacitance as function of the drain–source voltage ($V_\text{ds}$) for zero gate-source voltage ($V_{\text{gs}}$) can be measured on standard impedance analyzers and are specified in the datasheet of the respective device. The lumped equivalent interterminal capacitances, $C_\text{gs}$, $C_\text{gd}$, and $C_\text{ds}$, of compact models are then typically derived from measured $C_\text{oss}$, $C_\text{iss}$, and $C_\text{rss}$ characteristics, as $C_\text{oss}$ = $C_\text{gd}$+ $C_\text{ds}$, $C_\text{iss}$ = $C_\text{gd}$+ $C_\text{gs}$, and $C_\text{gd}$ = $C_\text{rss}$.
The importance of considering that the mosfet C–V characteristics depend on both $V_\text{ds}$ and $V_\text{gs}$ for modeling was reported in [5], [8]–[11], showing that the capacitance trajectories during turn-on and turn-off transients differ from the C–V curves derived dependent on $V_\text{ds}$ only. Accordingly, the C–V characterization of power mosfets goes beyond the measurements of $C_\text{oss}(V_{\text{ds}}$), $C_\text{iss}(V_{\text{ds}}$), and $C_\text{rss}(V_{\text{ds}}$) at $V_{\text{gs}} = 0$. Since power mosfets are controlled by $V_{\text{gs}}$, the $V_{\text{gs}}$ dependence of $C_\text{gs}$ and $C_\text{gd}$ should be evaluated in addition to their $V_{\text{ds}}$ dependence. The $V_\text{gs}$-dependent characteristics of $C_\text{gs}$ and $C_\text{gd}$ at $V_\text{ds}=$ 0 V, used in compact models as shown in, e.g., [4], [12]–[16], are often not consistent in the full range of $V_\text{gs}$ with the relation $C_\text{iss} = C_\text{gs}+C_\text{gd}$ resulting from the lumped electrical equivalent circuit of a power mosfet depicted in Fig. 1. As consequence, $C_\text{gs}$ and $C_\text{gd}$ are modeled incorrectly, which leads to inaccurate simulations of switching transients.
A sophisticated measurement setup for C–V characterization of high-voltage power devices beyond datasheets was shown in [17]. The accuracy of the proposed measurement setup was assessed by capacitance measurements of three test capacitors connected in the same delta configuration as the voltage-dependent mosfet interterminal capacitances, $C_\text{gs}$, $C_\text{gd}$, and $C_\text{ds}$. However, such a measurement setup only imitates the mosfet equivalent circuit in the off-state, i.e., at $V_{\text{gs}}$ below the threshold voltage ($V_\text{th}$). Additionally, the C–V measurements were shown only for Si-IGBTs. The difference between Si and SiC power mosfets with respect $C_\text{gd}(V_\text{gs}$) and $C_\text{gs}(V_\text{gs}$) was explained in [18]; however, neither the measurement setup nor the devices under test were shown. Namely, for a strong channel inversion, i.e., $V_\text{gs} \gg V_\text{th}$, $C_\text{gd}$ of SiC power mosfets is in the range of $C_\text{gs}$, while for Si power mosfets, $C_\text{gs} \gg C_\text{gd}$. As a consequence, $C_\text{gs}$ and $C_\text{gd}$ measurements of SiC power mosfets are more sensitive to gate current sharing between the source and the drain current paths in the $V_{\text{gs}}$ measurement range and it has to be ensured that a measurement setup does not affect this current sharing.
Accordingly, this article focuses on the characterization of $C_\text{iss}(V_{\text{gs}}$), $C_\text{gs}(V_{\text{gs}}$), and $C_\text{gd}(V_{\text{gs}}$) in the range of ($V_{\mathrm{gs,off}}$, $V_{\mathrm{gs,on}}$), where $V_{\mathrm{gs,off}}$ and $V_{\mathrm{gs,on}}$ are the maximum recommended turn-off and turn-on gate-source control voltages. This is of high importance for emerging SiC power mosfets with respect to 1) designing the gate circuit [12], [19], 2) evaluating gate bias instability [20], 3) extracting electrically active traps and defects at the MOS interface [21]–[23], and 4) parametrization of compact device models by including $V_\text{gs}$-dependent capacitance models, as suggested in [4], [5], [14], [15], [24].
The article is organized as follows. In Section II, a theoretical background of the commonly used relationship between $C_\text{iss}$, $C_\text{gs}$, and $C_\text{gd}$ is given and the $V_{\text{gs}}$ dependence of $C_\text{iss}$, $C_\text{gs}$, and $C_\text{gd}$ is briefly explained starting from the lumped equivalent circuit of a power mosfet. In Section III, the requirements on the measurement setup for accurate C–V characterization are described. An analytical description of $C_\text{gd}$ and $C_\text{gs}$ as function of the circuit parameters of the equivalent power mosfet model is derived in Section V. Furthermore, based on this analytical model, a new method is proposed for extracting the ratio ($R_\text{ch}$/$R_\text{drift}$) between the mosfet’s on-state resistance ($R_{\mathrm{ds,on}}$) components, $R_\text{ch}$ and $R_\text{drift}$, based on the measurements of $C_\text{gd}$ and $C_\text{gs}$. In Section IV, the C–V measurement results of commercial off-the-shelf (COTS) Si and SiC power mosfets are analyzed showing the differences between Si and SiC power mosfets. Section VI addresses the selection of appropriate measurement instruments and a correct connection of the mosfet to the test fixture for accurate characterization of interterminal gate capacitances. Finally, Section VII concludes this article.
SECTION II.
Power Mosfet Lumped Equivalent Model
A. Power Mosfet Capacitance Relations
The gate, drain, and source terminals of a packaged power mosfet are denoted by G, D, and S, respectively, in the equivalent circuit shown in Fig. 1. DC bias voltages ($V_\text{ds}, V_\text{gs}$) and the drain, source conduction currents ($I_{\mathrm{d}}, I_{\mathrm{s}}$) are represented by capital, whereas time-dependent small-signal voltages ($v_{\mathrm{d}}$, $v_{\mathrm{s}}$, and $v_{\mathrm{g}}$) and charging currents ($i_{\mathrm{d}}$, $i_{\mathrm{s}}$, and $i_{\mathrm{g}}$) are denoted by lowercase symbols. The mosfet symbol ($M$) represents the voltage-controlled current source. The diode ($D_{\mathrm{b}}$) models the mosfet’s internal body-diode. The lumped resistors $R_\text{gg}$ represent the resistance of the mosfet’s distributed gate, whereas $L_{\mathrm{g}}, L_{\mathrm{d}}$, and $L_{\mathrm{s}}$ represent a simplified model of the package parasitic stray inductances [6]. The capacitors $C_\text{gs}$, $C_\text{gd}$, and $C_\text{ds}$ are defined according to
\begin{align*}
C_\text{ij}=&\frac{\partial q_{\mathrm{i}}}{\partial v_{\mathrm{j}}}|_{\mathrm{i=j}}\tag{1a}
\\
C_\text{ij}=&-\frac{\partial q_{\mathrm{i}}}{\partial v_{\mathrm{j}}}|_{\mathrm{i{\ne }j}} \tag{1b}
\end{align*}View Source
\begin{align*}
C_\text{ij}=&\frac{\partial q_{\mathrm{i}}}{\partial v_{\mathrm{j}}}|_{\mathrm{i=j}}\tag{1a}
\\
C_\text{ij}=&-\frac{\partial q_{\mathrm{i}}}{\partial v_{\mathrm{j}}}|_{\mathrm{i{\ne }j}} \tag{1b}
\end{align*}
where a capacitor $C_\text{ij}$ between the terminals drain, gate, and source, i.e., $i,j\in \lbrace \mathrm{d, g, s}\rbrace$, defines the change of charge $\partial q_{\mathrm{i}}$ at terminal i, induced by a change of potential $\partial v_{\mathrm{j}}$ at terminal j. $C_\text{ij}$ with $i=j$ are denoted as terminal capacitances (self-capacitance) and $C_\text{ij}$ with $i\ne j$ as interterminal capacitances (trans-capacitances). For the extraction of the equivalent lumped interterminal capacitances used in power mosfet compact models, typically their reciprocity, $C_\text{ds}=C_\text{sd}$, $C_\text{gd}=C_\text{dg}$, and $C_\text{gs}=C_\text{sg}$ [25]–[27], has been assumed. Based on (1a) and (1b), reciprocity, and the Kirchhoff’s system of equations for the power mosfet equivalent circuit shown in Fig. 1, the relationship between $C_\text{ij}$, $i,j\in \lbrace \mathrm{d, g, s}\rbrace$, $C_\text{oss}$, $C_\text{iss}$, and $C_\text{rss}$ can be derived [25], [27] as
\begin{align*}
C_\text{oss}=C_\text{dd}=&C_\text{gd}+C_\text{ds}\tag{2}
\\
C_\text{iss}=C_\text{gg}=&C_\text{gs}+C_\text{gd}\tag{3}
\\
C_\text{rss}=&C_\text{gd}. \tag{4}
\end{align*}View Source
\begin{align*}
C_\text{oss}=C_\text{dd}=&C_\text{gd}+C_\text{ds}\tag{2}
\\
C_\text{iss}=C_\text{gg}=&C_\text{gs}+C_\text{gd}\tag{3}
\\
C_\text{rss}=&C_\text{gd}. \tag{4}
\end{align*}
This article focuses on gate capacitance characterization based on relation (3) as function of $V_\text{gs}$ = $V_\text{gd}$. Thus, the notation $C_\text{gg}$ is used instead of $C_\text{iss}$ and the interterminal gate capacitances are denoted as drain-gate ($C_\text{dg}$) and source-gate ($C_\text{sg}$) according to (1b), as will be explained in more detail in Section III.
B. $V_\text{gs}$ Dependence of Power mosfet Capacitances
A power mosfet turns on or off by applying a gate-source voltage $V_\text{gs}$ above or below $V_\text{th}$, which in turn controls the charge carrier distribution at the oxide–semiconductor interface [28]. The channel of the power mosfet is closed for $V_\text{gs} < V_\text{th}$ and opened for $V_\text{gs} \geq V_\text{th}$. The equivalent electric circuits of turned-off and turned-on power mosfets are illustrated in Fig. 2(a) and (c), using a schematic for a half-cell structure of a vertical double-diffused power mosfet. The corresponding small-signal equivalent circuits of Fig. 2(a) and (c) are given in Fig. 2(b) and (d), indicating the voltage dependencies of the capacitances and resistances. In Fig. 2(a), the gate capacitance is split into the overlap capacitance $C_\text{ov2}$ between the gate and the source metallization, $C_\text{ov1}$ between the gate and the n+ contact, $C_\text{g1}(V_\text{gs})$ in series to $C_\text{ch}(V_\text{gs})$ of the mosfet channel, and $C_\text{g2}(V_\text{gs})$ connected to the JFET depletion capacitance $C_\text{JFET}(V_\text{ds}, V_\text{gs})$. Based on (3), the input capacitance $C_\text{gg}$ is divided into $C_\text{sg}$ composed of the sum of $C_\text{ov}=C_\text{ov1}$+$C_\text{ov2}$ and $C_\text{g1}$ in series to $C_\text{ch}$, whereas $C_\text{dg}$ consists of the series connection of $C_\text{g2}$ and $C_\text{JFET}$. $C_\text{ds}$ depicts the junction capacitance between the p base and the n drift layer, whereas $R_\text{Epi}(V_\text{ds}, V_\text{gs})$ and $R_\text{JFET}(V_\text{ds}, V_\text{gs})$ model the resistance of the epitaxial- (Epi-) and JFET-layer, respectively. This epitaxial layer is especially characteristic for SiC devices, where a low-doped high-quality crystalline layer is grown on a higher doped substrate. The sum of $R_\text{JFET}+R_\text{Epi}$ is denoted here for further use as drift resistance
\begin{equation*}
R_\text{drift}=R_\text{JFET}+R_\text{Epi}. \tag{5}
\end{equation*}View Source
\begin{equation*}
R_\text{drift}=R_\text{JFET}+R_\text{Epi}. \tag{5}
\end{equation*}
The resistance of the n+ substrate is accounted in $R_\text{Epi}$. The small resistances of the n+ source and package electrodes are neglected, as well as the resistance of the p base.
By applying $V_\text{gs} \geq V_\text{th}$, the depletion capacitance $C_\text{ch}$ in Fig. 2(a) changes into an inversion layer resistance $R_\text{ch}(V_\text{ds}, V_\text{gs})$ in Fig. 2(c), forming a channel between the n+ contact and the JFET region. A current conducting path between the drain and source contacts is formed by $R_\text{ch}$ in series with $R_\text{drift}$. At $V_\text{gs} > V_\text{th}$ and $V_\text{ds}=$ 0 V, $C_\text{JFET}$ is the accumulation capacitance in the JFET region, which is much larger than the oxide capacitance $C_\text{g2}$, and, therefore, can be neglected for the following discussion.
SECTION III.
Small-Signal Gate Characterization Methodology
Characterization of voltage-dependent mosfet capacitances is typically performed by two measurement methods. The first method, referred to as ramp rate technique in [29], is based on voltage ramp measurements in the time-domain, where the capacitance is extracted as $C=\frac{I}{dV/dt}$. The main challenge of ramp rate measurements is to keep the $dV/dt$ relatively low to minimize transient effects and, at the same time, avoid pronounced self-heating. Accordingly, the circuit layout of the measurement setup can have a significant impact on the C–V extraction.
The second approach is based on small-signal measurements [30] in the frequency domain ($\omega$), where C is extracted either from the complex impedance $\bar{Z}$ by using polar coordinates (mag($\bar{Z}$) = $|\bar{Z}|$, phase ($\bar{Z}$) = $\varphi (\bar{Z})$) as
\begin{equation*}
C_{\mathrm{s}}= \frac{-1}{\Im \lbrace \bar{Z}\rbrace \omega }= \frac{-1}{\omega |\bar{Z}|\text{sin}(\varphi (\bar{Z}))} \tag{6}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{s}}= \frac{-1}{\Im \lbrace \bar{Z}\rbrace \omega }= \frac{-1}{\omega |\bar{Z}|\text{sin}(\varphi (\bar{Z}))} \tag{6}
\end{equation*}
using a series-equivalent model $C_{\mathrm{s}}-R_{\mathrm{s}}$, or from the complex admittance $\bar{Y}$ as
\begin{equation*}
C_{\mathrm{p}}= \frac{\Im \lbrace \bar{Y}\rbrace }{\omega }= \frac{-\text{sin}(\varphi (\bar{Z}))}{\omega |\bar{Z}|} \tag{7}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{p}}= \frac{\Im \lbrace \bar{Y}\rbrace }{\omega }= \frac{-\text{sin}(\varphi (\bar{Z}))}{\omega |\bar{Z}|} \tag{7}
\end{equation*}
using a parallel-equivalent model $C_{\mathrm{p}}||G_{\mathrm{p}}$. From (6) and (7), the relation between $C_{\mathrm{s}}$ and $C_{\mathrm{p}}$ is found to be
\begin{equation*}
C_{\mathrm{s}}\text{sin}^{2}(\varphi (\bar{Z})) = C_{\mathrm{p}}. \tag{8}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{s}}\text{sin}^{2}(\varphi (\bar{Z})) = C_{\mathrm{p}}. \tag{8}
\end{equation*}
Equation (8) shows that the difference between $C_{\mathrm{s}}$ and $C_{\mathrm{p}}$ is solely caused by $\varphi (\bar{Z})$, i.e., by $\text{sin}^{2}(\varphi (\bar{Z})$.
Small-signal measurements are typically performed on standard impedance analyzers selecting a low dc bias sweep rate to accurately extract C–V characteristics. Moreover, to perform C–V measurements during the mosfet’s on state as function of both $V_\text{ds}$ and $V_\text{gs}$, external bias-Ts have to be added to the mosfet’s terminals [31], [32]. There, a trade-off between the small-signal measurement frequency and self-heating effects has to be considered [5].
To avoid the side effects of auxiliary measurement components (e.g., bias-Ts), the C–V characterization in this work is performed based on the small-signal method as function of $V_\text{gs}$ at $V_\text{ds}=$ 0 V, using a Keysight E4990A impedance analyzer. The Keysight E4990A is based on an autobalancing bridge measurement technique. It has a bias range of $\pm$40 V/$\pm$20 mA or $\pm$25 V/$\pm$100 mA and a frequency range of 20 Hz to 120 MHz. The test fixture Keysight 16047E rated for a maximum frequency range of 120 MHz is used to mount the DUTs. All DUTs are packaged in a TO-247 3-pin package. The 16047E allows the measurements of 3-, or 4-pin packaged power mosfets, which must be connected to its high-side (AC+), low-side (AC$-$), and guard (ACG) electrodes, respectively, as illustrated in Fig. 3. The advantage of the autobalancing bridge technique is that the current $i_\text{ac}$ on the the low-side AC$-$ is measured in the negative feedback loop after the common virtual ground potential [30], which eliminates the influence of the ampere meter on the measured current.
A. Electrical Equivalent Circuit of the Setup
The electrical equivalent circuit of this small-signal gate capacitance characterization setup is illustrated in Fig. 4. It includes the mosfet’s equivalent circuit introduced in Fig. 1. The high-side (AC+) of the small-signal voltage source ($v_\text{ac}$) and the dc bias voltage ($V_\text{DC}$) are superposed by the internal bias-T at the gate terminal. Both the drain and source terminals are connected to the dc ground potential ($V_\text{GND}$). The small-signal current ($i_\text{ac}$) is measured at the low-side (AC$-$) of $v_\text{ac}$, which is coupled to either the drain or the source terminal. The impedance $\bar{Z}=\bar{v}_\text{ac}/\bar{i}_\text{ac}$ is derived from the voltage $\bar{v}_{\mathrm{ac^{+}-ac^{-}}}$ measured across AC+ and AC-, and the current $\bar{i}_\text{ac}$ at AC-. Hereafter, complex impedances ($\bar{Z}$), voltages ($\bar{v}$), and currents ($\bar{i}$) will be denoted without macron for simplicity.
Setting up the measurements of the interterminal capacitances $C_\text{ij}|_{\mathrm{(i\ne j)}}$ of 3-, or 4-pin packaged power mosfets require a special attention. The third terminal of the mosfet must be connected to ac guard (ACG) [33], in order to avoid capacitive coupling over the floating third terminal in parallel to $C_\text{ij}$.
$Z_{\mathrm{g}}, Z_{\mathrm{d}}$, and $Z_{\mathrm{s}}$ in Fig. 4 represent the stray impedances of the setup connections AC+, AC$-$, and ACG, including $L_{\mathrm{g}}, L_{\mathrm{d}}$, and $L_{\mathrm{s}}$ of the DUT package depicted in Fig. 1. These impedances influence the measurement of Z between AC+–AC$-$, since they are connected in series with the DUT terminals.
B. Extraction of $C_\text{gg}$
For the extraction of the input capacitance $C_\text{gg}$, defined by (1a), the gate terminal is connected to AC+, and the drain and source terminals are connected both to AC$-$, so that the sum of the currents $i_\text{gd}$ and $i_\text{gs}$ is measured at AC$-$; see Fig. 4. According to the mosfet’s equivalent circuit, a series-equivalent model $C_{\mathrm{s}}-R_{\mathrm{s}}$ is intuitively used to model the gate circuit, and hence, the $C_{\mathrm{s}} - R_{\mathrm{s}}$ model was used to extract $C_\text{gg}$ from the imaginary part of the input impedance $Z_\text{gg}$ based on (6), whereas the real part $\Re \lbrace Z_\text{gg}\rbrace$ can be used to extract the lumped equivalent gate resistance, $R_\text{gg}$. The $Z_\text{gg}$ measurements of a planar-gate SiC power mosfet M1, listed in Table I, is used here as an example to better explain the recommended measurement settings for the $C_\text{gg}$ extraction. The magnitude-phase measurements of $Z_{\mathrm{gg,M1}}$ are presented in Fig. 5 for $V_\text{gs}=$ 0 V and $V_\text{gs}=$ 20 V.
At high frequencies > 1 MHz, a series-equivalent model has to be extended to a $C_{\mathrm{s}}-R_{\mathrm{s}}-L_{\mathrm{s}}$ equivalent model, where $L_{\mathrm{s}}$ is used to explain the $Z_\text{gg}$ resonance in Fig. 5. Namely, the inductive reactance $X=\omega L$ determined by the package parasitic inductances, which in turn depends on the length of the package pins above the test fixture, shifts the phase of $Z_\text{gg}$ positively [34]. Accordingly, the input capacitance $C_\text{gg}$ is preferably measured at lower frequencies, e.g., 30 kHz, to reduce $X=\omega L$, and to achieve a high measurement accuracy, i.e., $0.1\, \%$ accuracy of the measurement instrument is specified for $|Z_\text{meas}|$ in the range of (1 –100 k$\Omega$) [35].
At the resonance frequency ($f_\text{res}$), the magnitude of the measured impedance ($Z_\text{meas}$) $|Z_\text{meas}|$ = $\Re \lbrace Z_\text{meas}\rbrace$. Hence, $|Z_\text{gg}(f_\text{res})|$ represents the lumped value of the internal gate resistance of the mosfet’s compact model. For the $Z_{\mathrm{gg,M1}}$ two resonance frequencies ($\varphi =$ 0 deg) can be observed for $V_\text{gs}=$ 0 V, which can be simulated using a mosfet compact model equivalently to Fig. 1. For $V_\text{th} \ll V_\text{gs}=$ 20 V, only a single resonance peak appears, since the open channel of the mosfet almost provides an AC short of the internal drain–source contacts and leads to a series-equivalent connection of $(R-C-L) \approx L_{\mathrm{g}}-R_\text{gg}-C_\text{gg}-L_{\mathrm{d}}||L_{\mathrm{s}}$; see Fig. 2(c) and (d). Therefore, for $V_\text{gs} \gg V_\text{th}$, e.g. $V_\text{gs}=$ 20 V, the direct extraction of measured $\Re \lbrace Z_\text{gg}\rbrace =R_\text{gg}$ is possible, which is not necessarily true for $V_\text{gs}=$ 0 V.
Both $C_\text{gg}$ and $R_\text{gg}$ are frequency-dependent. For example, $R_\text{gg}(V_\text{gs}= \mathrm{\text{20}\,V})$ shows a difference of +44 % between the values of 2.37 $\Omega$ at $f=$ 38.5 MHz and 3.42 $\Omega$ at $f=$ 1 MHz. The main contribution at higher frequencies above 1 MHz is due to the distributed $R_\text{gg}-(C_\text{gg}||G_{\mathrm{p}})$ (parallel conductance $G_{\mathrm{p}}$) behavior of the mosfet’s distributed gate layout [36] and package parasitics. The frequency dependence of $C_\text{gg}$ for frequencies below 1 MHz is very small, whereas $R_\text{gg}$ might be strongly affected by oxide interface states, gate leakage current, and insufficient accuracy of the $Z_\text{gg}$ phase measurement. However, the detailed discussion of such frequency dependence is not in focus of this article and, hence, is omitted for the sake of brevity.
C. Extraction of $C_\text{dg}$ and $C_\text{sg}$
In a $C_\text{dg}$ measurement, the mosfet’s D and S terminals are connected to AC$^\mathrm{-}$ and ACG, respectively (see Fig. 4), where $Z_{\mathrm{s}}=j\omega L_{\mathrm{s}}+Z_\text{ACG}$ and $Z_{\mathrm{d}}=j\omega L_{\mathrm{d}} + Z_{\mathrm{AC^\mathrm{-}}}$. In contrast, in a $C_\text{sg}$ measurement the D and S terminals are connected to ACG and AC$^\mathrm{-}$, respectively, so that $Z_{\mathrm{s}}=j\omega L_{\mathrm{s}}+Z_{\mathrm{ac^\mathrm{-}}}$ and $Z_{\mathrm{d}}=j\omega L_{\mathrm{d}} + Z_\text{ACG}$. The ampere meter (A) (always at AC$^\mathrm{-}$ of the Keysight E4900A), which is located in the current path of $i_{\mathrm{d}}$ for $C_\text{dg}$ or in the current path of $i_{\mathrm{s}}$ for $C_\text{sg}$, indicates the position at which $i_{\mathrm{d}}$ or $i_{\mathrm{s}}$ are measured.
The small-signal voltage $v_\text{ds}$ between AC$^\mathrm{-}$/ACG and the DC bias voltage $V_\text{ds}$ are ideally equal to 0 V. However, it will be shown that the effective condition $V_\text{ds}\ne \text{0}\,V$ has significant impact on the measurement of the interterminal drain-gate impedance, $Z_\text{dg}$, and source-gate impedance, $Z_\text{sg}$, from which $C_\text{dg}$ and $C_\text{sg}$ are extracted based on (7) or (6), respectively.
During $Z_\text{dg}$ and $Z_\text{sg}$ measurements, the small-signal current $i_{\mathrm{g}}$ is divided into two components, $i_{\mathrm{d}}$ and $i_{\mathrm{s}}$, flowing into the drain and source terminals, respectively.
Starting from the mosfet’s small-signal equivalent circuit shown in Fig. 2(b), the $i_{\mathrm{d}} = -i_\text{gd}$ path in the off-state is via $C_\text{g2}, C_\text{JFET}$, and $R_\text{JFET}$, while the current path of $i_{\mathrm{s}}=-i_\text{gs}$ is defined by $C_\text{g1} || C_\text{ov}$. The current path between the drain and source terminals is split into the channel current, $i_\text{ch}$, which is 0 A in the off-state, and the current $i_\text{ds}$ via $C_\text{ds}$. The voltage difference across $C_\text{ds}$ and the current $i_\text{ds}$ can be neglected since 1) the impedances $|Z_{\mathrm{d}}+R_\text{Epi}|, |Z_{\mathrm{s}}| \ll 1/(\omega C_\text{dg}), 1/(\omega C_\text{sg})$, $1/(\omega C_\text{ds})$ at frequencies $f < $ 10 MHz ($C_\text{ij} \sim \text{1}\,nF$ and $R_\text{Epi} \leq 1\,\Omega$), hence, the corresponding voltages $|v_\text{ac}| \gg |i_{\mathrm{d}}(Z_{\mathrm{d}}+R_\text{Epi})|\approx |i_{\mathrm{s}}Z_{\mathrm{s}}| \approx$ 0 V, and 2) $v_\text{ac} \gg v_\text{ds}$ between AC$^\mathrm{-}$/ACG $\approx$ 0 V.
The small-signal electrical equivalent circuits of the measurement setups for $C_\text{dg}$ and $C_\text{sg}$ in the on-state are shown in Fig. 6(a) and (b). The power mosfet model for the condition of a strong inversion is shown in Fig. 2(d), based on which the interterminal gate capacitances are defined as
\begin{align*}
C_{\mathrm{dg,on}}& =C_\text{g2}\tag{9}
\\
C_{\mathrm{sg,on}}& = C_\text{g1}+C_\text{ov}. \tag{10}
\end{align*}View Source
\begin{align*}
C_{\mathrm{dg,on}}& =C_\text{g2}\tag{9}
\\
C_{\mathrm{sg,on}}& = C_\text{g1}+C_\text{ov}. \tag{10}
\end{align*}
During measurements, the gate current $i_{\mathrm{g}}$ is divided into $i_\text{ov}$, flowing through the overlap capacitance $C_\text{ov}$, and into $i_{\mathrm{g^{\prime }}}=i_{\mathrm{g}}-i_\text{ov}$, flowing through the parallel capacitances $C_\text{g1}$ and $C_\text{g2}$, which is defined here as
\begin{equation*}
C_{\mathrm{g^{\prime }}}=C_\text{g1}+C_\text{g2}=C_\text{gg}-C_\text{ov}. \tag{11}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{g^{\prime }}}=C_\text{g1}+C_\text{g2}=C_\text{gg}-C_\text{ov}. \tag{11}
\end{equation*}
In addition to the terminal currents $i_{\mathrm{d}}$ and $i_{\mathrm{s}}$, a current source $i_{\mathrm{g_{ch}}}$ needs to be modeled in parallel to $R_\text{ch}$. This current source $i_{\mathrm{g_{ch}}}$ results due to the mosfet’s channel transconductance ($g_\text{ch}$) [26]. Since the total transconductance $g_{\mathrm{m}}$ is mainly determined by $g_\text{ch}$, the contributions of the JFET- and Epi-layer transconductances are neglected here for the sake of simplicity. The transconductance $g_{\mathrm{m}}$ of M1 obtained from quasi-static $I_{\mathrm{d}}-V_\text{gs}$ measurements is shown for $V_\text{ds}=$ 50 mV and $V_\text{ds}=$ 0 V in Fig. 7(a).
During measurements of $Z_\text{dg}$ and $Z_\text{sg}$ for $V_\text{gs} \geq V_\text{th}$, the product of the internal gate-source voltage $v_\text{gs}$ (across the oxide/semiconductor interface) and $g_\text{ch}$, where $g_\text{ch} \sim V_\text{ds}$ for small $V_\text{ds}$, leads to a current flow $i_{\mathrm{g_{ch}}} = g_\text{ch}v_\text{gs}$ (in phase with $v_\text{gs}$) between the drain-source terminals (AC $^\mathrm{-}$/ACG) in the case of $V_\text{ds}\ne$ 0 V. This current flow only occurs due to the failure of guarding [30], when the open mosfet channel creates a low-resistive connection ($R_{\mathrm{ds,on}}$) between AC$^\mathrm{-}$ and ACG. This is demonstrated in the following on the example of the planar-gate SiC power mosfet, M1, listed in Table I. Finite values of $V_\text{ds}$ were measured in the range of 350 –50 $\mu$V with the digital multimeter Keithley DMM6500 [37] for $ V_\text{th} < V_\text{gs} \leq$ 20 V. The product of this measured $V_\text{ds}$ and normalized transconductance $g_{\mathrm{m, norm}}$ ($g_{\mathrm{m,norm}}V_\text{ds}$), where $g_{\mathrm{m, norm}} = g_{\mathrm{m}}/({\mathrm{\text{50}\,mV})}$ [as measured in Fig. 7(a)], is compared with the absolute conductance $|G_\text{sg}|$ and $\omega C_{\mathrm{sg,s}}$ from the $Z_\text{sg}$ measurement. The conductance peak of $g_{\mathrm{m,norm}}V_\text{ds}$ clearly correlates with the peak of $|G_\text{sg}|$ and $\omega C_\text{sg}$, as shown in Fig. 7(b).
The effect of $i_{\mathrm{g_{ch}}}= g_\text{ch}v_\text{gs}$ results mainly in a deviation of the phase $Z_\text{dg}$ ($\varphi (Z_\text{dg})$) and the phase $Z_\text{sg}$ ($\varphi (Z_\text{sg})$) from $-$90 deg, as shown in Fig. 8(a), at $f =$ 30 kHz. Note that $\varphi (Z_\text{dg})$ and $\varphi (Z_\text{sg})$ deviate from $-$90 deg starting from $V_\text{gs} \approx V_\text{th}$ and reach a negative peak value of $-$141 and $-$137 deg, respectively. This value of deviation from $-$90 deg is proportional to $g_\text{ch}$ and, hence, to $V_\text{ds}$, i.e., the voltage between AC$^\mathrm{-}$ and ACG. With increasing frequency, the amplitudes of $i_{\mathrm{d}}=v_\text{ac}/Z_\text{dg}$ and $i_{\mathrm{s}}=v_\text{ac}/Z_\text{sg}$ increase for a constant value of $v_\text{ac}$ due to the reduction of $|Z_\text{dg}| \approx |\frac{1}{\omega C_\text{dg}}|$, $|Z_\text{sg}|\approx |\frac{1}{\omega C_\text{sg}}|$. As a result, the ratios of $|i_{\mathrm{d}}|/|i_{\mathrm{g_{ch}}}|$, $|i_{\mathrm{s}}|/|i_{\mathrm{g_{ch}}}|$ increase with increasing frequency until $|i_{\mathrm{d}}|$, $|i_{\mathrm{s}}| \gg |i_{\mathrm{g_{ch}}}|$, for which the influence of $g_\text{ch}v_\text{gs}$ becomes negligible.
The impact of this phenomena ($i_{\mathrm{g_{ch}}} = g_\text{ch}v_\text{gs}$) is further analyzed by the extraction of $C_\text{dg}$ and $C_\text{sg}$ using both series- and parallel-equivalent circuits and (6) and (7), respectively. It should be noted that a series-equivalent circuit is typically selected since the equivalent circuits of the gate current paths can be described by a series connection of resistance and capacitance, without prior knowledge of the distortions introduced by the measurement setup. Fig. 8(b) and (c) shows the parallel ($C_{\mathrm{p}}$) and series ($C_{\mathrm{s}}$) equivalent capacitances for $C_\text{dg}$ and $C_\text{sg}$, which are extracted from $Z_\text{dg}$ and $Z_\text{sg}$ of Fig. 8(a). The comparison between $C_{\mathrm{p}}$ and $C_{\mathrm{s}}$ shows that the deviations in $\varphi (Z_\text{dg})$ and $\varphi (Z_\text{sg})$ only affect $C_{\mathrm{s}}$, indicated by the capacitance peaks in Fig. 8(b) and (c). The extracted parallel capacitances $C_{\mathrm{p}}$ of $C_\text{dg}$ and $C_\text{sg}$ are not affected by these phase distortions, even though $C_{\mathrm{p}}$ is extracted from the same impedance as $C_{\mathrm{s}}$.
This is explained by the parallel-equivalent circuit used for the extraction of $C_{\mathrm{p}}$ in (7). The transconductance contributes only to the in-phase current represented by the parallel conductance $G_{\mathrm{p}}$ (the real part of the admittance $Y=1/Z$) and, therefore, leaves $C_{\mathrm{p}}$ unaffected. On the contrary, the series-equivalent model $R_{\mathrm{s}}-C_{\mathrm{s}}$ cannot correctly represent this effect, since the in-phase current $i_{\mathrm{g_{ch}}}=g_\text{ch}v_\text{gs}$ ($\varphi (i_{\mathrm{g_{ch}}}) = 0\,^\circ$) would lead to an increase of the differential capacitance $C_{\mathrm{s}}$ by $\Delta C \sim \partial q/\partial v_\text{gs} \sim i_{\mathrm{g_{ch}}}/(\omega v_\text{gs}) \sim g_\text{ch}/f$, resulting in the observed capacitance peak, which does not correctly represent the underlying device physics. Thus, $C_\text{dg}$ and $C_\text{sg}$ should be extracted from the measured impedances $Z_\text{dg}$, $Z_\text{sg}$ or admittance $Y_\text{dg}$, $Y_\text{sg}$ as parallel equivalent capacitance $C_{\mathrm{p}}$.
Another interesting observation is the deviation of $\varphi (Z_\text{dg})$ from $-$90 deg toward increasing negative values for decreasing $V_\text{gs} \leq$ $-$5 V, as depicted in Fig. 8(a). This effect is not due to the failure in guarding between AC$^\mathrm{-}$ and ACG, but it can be explained by the formation of an inversion layer of holes at the oxide–JFET interface, cf. Fig. 2(a). This inversion layer of holes forms a resistive connection between the oxide–JFET interface and the p base [38], while it is separated by a depletion region from the conducting Epi-layer of the drain current path. As a result, a part of the current $i_\text{ac}$ ($i_{\mathrm{g^{\prime }}}$) is bypassed through the p base into the source instead of the drain terminal, which causes this deviation in $\varphi (Z_\text{dg})$ for negative $V_\text{gs}$.
SECTION IV.
C–V Measurement Results
In this section, the measurement results of gate capacitance characteristics are presented for SiC and Si power mosfets. The measurements are performed at $f=$ 30 kHz and at room temperature ($T=$ 25 $^\circ$C) if not otherwise stated. The properties of the DUTs, such as label, type, $V_\text{ds}$ rating, nominal drain current $I_{\mathrm{d}}$, and on-state resistance $R_{\mathrm{ds,on}}$, are listed in Table I.
Prior to all measurements, open- and short- compensation of the test fixture were performed. During each measurement, $V_\text{gs}$ was swept from negative to positive polarity with a point delay of 1 s.
$C_\text{gg}$ measurements at $f=$ 30 kHz, $f=$ 100 kHz, and $f=$ 1 MHz of two SiC (M1,M2) and two Si (M3, M4) power mosfets are shown in Fig. 9. Only a small frequency dependence is visible, except for M2, which shows a difference of up to 7.5 % for $V_\text{gs}< $$-$5 V at f = 1 MHz in comparison to $f=$ 30 kHz and $f=$ 100 kHz.
The frequency dependence of $C_{\mathrm{sg,M1}}$ and $C_{\mathrm{dg,M1}}$ is shown in Fig. 10(a) and (b), respectively, for $f=\lbrace$30 kHz, 100 kHz, 1 MHz$\rbrace$. At $f=$ 30 kHz (black) and $f=$ 100 kHz (red), a difference is observable in $C_\text{dg}$ of up to 10 % at $V_\mathrm{{gs}}=$ 20 V, whereas $C_\text{sg}$ differs only by 1 %. Yet, $C_\text{dg}$ at $f=$ 1 MHz is higher by (112 %) and $C_\text{sg}$ lower by (30 %) in comparison to $f=$ 30 kHz.
The characteristics of $C_{\mathrm{dg,M1}}$ and $C_{\mathrm{sg,M1}}$ at $f=$ 30 kHz measured at $T=$ $\lbrace$25 $^\circ$C, 125 $^\circ$C, 175 $^\circ$C$\rbrace$ are shown in Fig. 11(a) and (b). The $C_\text{dg}$ decreases and the $C_\text{sg}$ increases with increasing temperature, which is due to the temperature dependance of the on-state resistance components, $R_\text{ch}(T)$ and $R_\text{drift}(T)$ [39], as it is further explained in Section V. In addition, a reduction of $V_\text{th}$ (the value of $V_\text{gs} >$ 0 V at which the curves for different temperatures start to diverge) is observable at the onset of inversion for $T=$ 125 $^\circ$C and $T=$ 175 $^\circ$C. The $V_\text{th}$ values of each DUT at room temperature are specified in Table II for the conditions of $V_\text{gs}=V_\text{ds}$ and $I_{\mathrm{d}}=$ 5 mA.
The gate capacitance characteristics $C_\text{gg}$ ($C_{\mathrm{s}}$) and $C_\text{dg}$, $C_\text{sg}$ ($C_{\mathrm{p}}$) of M1 are plotted in solid lines as functions of $V_\text{gs}$ at $V_\text{ds}=$ 0 V, for $f=$ 30 kHz and $f=$ 1 MHz in Fig. 12.
The measurement accuracy of $C_\text{dg}$ and $C_\text{sg}$ can be verified by comparing ($C_\text{dg}+C_\text{sg}$) with $C_\text{gg}$ according to (3). In the case of M1, ($C_\text{dg}+C_\text{sg}$) matches $C_\text{gg}$ at $f=$ 30 kHz, as shown in Fig. 12. On the other hand, the ($C_\text{dg}+C_\text{sg}$) measured at $f=$ 1 MHz starts to diverge from $C_\text{gg}$ for $V_\text{gs} > V_\text{th}$ up to a relative difference of 3.6 % at $V_\text{gs}=$ 20 V. This difference is caused by an increase of $|Z_{\mathrm{d}}| \sim wL_{\mathrm{d}}$ and $|Z_{\mathrm{s}}| \sim wL_{\mathrm{s}}$ of the package parastic inductances at $f=$ 1 MHz ($L_{\mathrm{d}} \ne L_{\mathrm{s}}$ [34], [40]), which leads to an increase of $C_\text{dg}$ and a decrease of $C_\text{sg}$, as shown in Fig. 10(a) and (b), respectively.
A. Comparison of SiC vs. Si Power mosfets
A comparison between the measured input capacitance $C_\text{gg}$ (solid lines) and ($C_\text{dg}+C_\text{sg}$) (dashed lines) is shown in Fig. 13 for Si- and SiC-power mosfets specified in Table I. For all DUTs, the extracted ($C_\text{dg}+C_\text{sg}$) match the extracted $C_\text{gg}$, which verifies the accuracy of the proposed measurement procedure.
The measured $C_\text{sg}$ and $C_\text{dg}$ of all DUTs are plotted in Figs. 14 and 15, respectively. For large negative $V_\text{gs}$, the JFET region below the gate oxide is in inversion, resulting in a very small depletion capacitance $C_\text{JFET}$, as depicted in Fig. 2(a), and hence, $C_\text{dg}$ is small [18]. $C_\text{dg}$ increases with increasing $V_\text{gs}$ corresponding to the change from inversion to accumulation and reaches the highest value for $V_\text{gs}$ around $V_\text{th}$. $C_\text{sg}$ is equal to $C_\text{gg}$ until the channel region starts to deplete. For $V_\text{gs} \geq V_\text{th}$, $C_\text{sg}$ increases.
The main difference between Si and SiC power mosfets in terms of $C_\text{sg}$ and $C_\text{dg}$ characteristics is apparent in strong inversion: While the $C_\text{sg}$ values in inversion and accumulation are very close for Si power devices, the inversion and accumulation values of $C_\text{sg}$ are different for SiC power mosfets. With respect to the $C_\text{dg}$ characteristics in inversion, it can be observed that the values of $C_\text{dg}$ are much smaller than $C_\text{sg}$ for Si power devices. On the other hand, $C_\text{dg}$ of SiC power mosfets is of the same order as $C_\text{sg}$ in inversion. This difference between Si and SiC power mosfets can be further explained by the following analysis based on an analytical derivation of $C_\text{dg}$ and $C_\text{sg}$, shown in Section V-B.
SECTION V.
A Proposed Method for the Extraction of $R_\mathrm{{ds,on}}$ Mosfet Components
In this section, a new method for the extraction of $R_\mathrm{{ds,on}}$ mosfet components is presented. First, analytical models of $C_\text{sg}$ and $C_\text{dg}$ are derived as function of the mosfet’s equivalent circuit parameters of Fig. 6(a) and (b), similar to the procedure presented in [26]. However, in [26], analytical models for $C_\text{gd}/C_\text{dg}$ and for $C_\text{gs}/C_\text{sg}$ were derived based on a small-signal equivalent circuit of a double-diffused mosfet, but without considering the mosfet’s overlap capacitance $C_\text{ov}$ and without the series impedances $Z_{\mathrm{s}}$, $Z_{\mathrm{d}}$ of the measurement setup.
The derivation presented here illustrates the differences between the parallel ($C_{\mathrm{p}}||G_{\mathrm{p}}$) and series ($C_{\mathrm{s}}-R_{\mathrm{s}}$) equivalent capacitance models.
A. Analytical Derivation of $C_\text{dg}$ and $C_\text{sg}$
The electrical equivalent circuits in Fig. 6(a) and (b) are solved by Kirchhoff’s circuit laws for the terminal currents $i_{\mathrm{d}}$ and $i_{\mathrm{s}}$. Based on the solutions of $i_{\mathrm{d}}$ and $i_{\mathrm{s}}$, the applied voltage $(v_{\mathrm{AC^+}}-v_{\mathrm{AC^-}})$, and the parallel-equivalent model (7), the interterminal capacitances can be derived by
\begin{equation*}
C_{\mathrm{dg,p}}=-\Im \left\lbrace \frac{-i_{\mathrm{d}}}{v_{\mathrm{AC^+}}-v_{\mathrm{AC^-}}}\right\rbrace /\omega \tag{12}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{dg,p}}=-\Im \left\lbrace \frac{-i_{\mathrm{d}}}{v_{\mathrm{AC^+}}-v_{\mathrm{AC^-}}}\right\rbrace /\omega \tag{12}
\end{equation*}
and
\begin{equation*}
C_{\mathrm{sg,p}}=-\Im \left\lbrace \frac{-i_{\mathrm{s}}}{v_{\mathrm{AC^+}}-v_{\mathrm{AC^-}}}\right\rbrace /\omega. \tag{13}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{sg,p}}=-\Im \left\lbrace \frac{-i_{\mathrm{s}}}{v_{\mathrm{AC^+}}-v_{\mathrm{AC^-}}}\right\rbrace /\omega. \tag{13}
\end{equation*}
In order to derive analytical forms of $C_{\mathrm{dg,p}}$ (12) and $C_{\mathrm{sg,p}}$ (13), the following assumptions of the small-signal circuit elements in Fig. 6(a) and (b) are used:
$1/(\omega C_{\mathrm{g^{\prime }}})$, $1/(\omega C_\text{ov})$, $1/(\omega C_\text{ds}) \gg R_\text{ch}$, $R_\text{drift}$, $|Z_{\mathrm{d}}|$, $|Z_{\mathrm{s}}|$
$C_{\mathrm{g^{\prime }}}$, $C_\text{ov}$, $R_\text{ch}$, $R_\text{drift}$, $|Z_{\mathrm{d}}|$, $|Z_{\mathrm{s}}|\leq 1$
$1/(\omega C_\text{gg}) \gg R_\text{gg}+|Z_{\mathrm{g}}|$.
\begin{align*}
C_{\mathrm{dg,p}}=\Re \lbrace (C_\text{ov}&(1+g_\text{ch}R_\text{ch})(Z_{\mathrm{s}}(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})+C_{\mathrm{g^{\prime }}}(R_\text{ch}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}Z_{\mathrm{s}}) \\
&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}(R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})))/ \\
&\qquad \qquad \qquad \qquad \qquad \qquad (R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+R_\text{ch}(1+g_\text{ch}Z_{\mathrm{s}}))^{2}\rbrace \tag{14}
\\
C_{\mathrm{sg,p}}= \Re \lbrace (C_\text{ov}&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}})(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})+C_{\mathrm{g^{\prime }}}(R_\text{drift}+Z_{\mathrm{d}}) \\
&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}(R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})))/ \\
&\qquad \qquad \qquad \qquad \qquad \qquad (R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+R_\text{ch}(1+g_\text{ch}Z_{\mathrm{s}}))^{2}\rbrace. \tag{15}
\end{align*}View Source
\begin{align*}
C_{\mathrm{dg,p}}=\Re \lbrace (C_\text{ov}&(1+g_\text{ch}R_\text{ch})(Z_{\mathrm{s}}(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})+C_{\mathrm{g^{\prime }}}(R_\text{ch}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}Z_{\mathrm{s}}) \\
&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}(R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})))/ \\
&\qquad \qquad \qquad \qquad \qquad \qquad (R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+R_\text{ch}(1+g_\text{ch}Z_{\mathrm{s}}))^{2}\rbrace \tag{14}
\\
C_{\mathrm{sg,p}}= \Re \lbrace (C_\text{ov}&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}})(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})+C_{\mathrm{g^{\prime }}}(R_\text{drift}+Z_{\mathrm{d}}) \\
&(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+g_\text{ch}R_\text{ch}(R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}})))/ \\
&\qquad \qquad \qquad \qquad \qquad \qquad (R_\text{drift}+Z_{\mathrm{d}}+Z_{\mathrm{s}}+R_\text{ch}(1+g_\text{ch}Z_{\mathrm{s}}))^{2}\rbrace. \tag{15}
\end{align*}
The solutions of (12) and (13) based on the Assumptions 1–3 are given in (14) and (15), shown at the bottom of this page. Here, two approximations for $C_{\mathrm{dg,p}}$ and $C_{\mathrm{sg,p}}$ are presented from (14) and (15). In the first approximation A1, $g_\text{ch}=$ 0 S is assumed, based on which $C_{\mathrm{dg,on,p}}$ and $C_{\mathrm{sg,on,p}}$ can be expressed in on-state as
\begin{align*}
&C_{\mathrm{dg,on,p}} |_{g_\text{ch}=0} \\
&\qquad \qquad \approx \Re \left\lbrace \frac{C_\text{ov}Z_{\mathrm{s}}+C_{\mathrm{g^{\prime }}}(R_\text{ch}+Z_{\mathrm{s}})}{R_\text{drift}+R_\text{ch}+Z_{\mathrm{d}}+Z_{\mathrm{s}}}\right\rbrace \tag{16}
\\
&C_{\mathrm{sg,on,p}} |_{g_\text{ch}=0} \\
&\approx \Re \left\lbrace \frac{C_{\mathrm{g^{\prime }}}(R_\text{drift}+Z_{\mathrm{d}})+C_\text{ov}(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}})}{R_\text{drift}+R_\text{ch}+Z_{\mathrm{d}}+Z_{\mathrm{s}}}\right\rbrace. \tag{17}
\end{align*}View Source
\begin{align*}
&C_{\mathrm{dg,on,p}} |_{g_\text{ch}=0} \\
&\qquad \qquad \approx \Re \left\lbrace \frac{C_\text{ov}Z_{\mathrm{s}}+C_{\mathrm{g^{\prime }}}(R_\text{ch}+Z_{\mathrm{s}})}{R_\text{drift}+R_\text{ch}+Z_{\mathrm{d}}+Z_{\mathrm{s}}}\right\rbrace \tag{16}
\\
&C_{\mathrm{sg,on,p}} |_{g_\text{ch}=0} \\
&\approx \Re \left\lbrace \frac{C_{\mathrm{g^{\prime }}}(R_\text{drift}+Z_{\mathrm{d}})+C_\text{ov}(R_\text{ch}+R_\text{drift}+Z_{\mathrm{d}})}{R_\text{drift}+R_\text{ch}+Z_{\mathrm{d}}+Z_{\mathrm{s}}}\right\rbrace. \tag{17}
\end{align*}
In the second approximation A2, $Z_{\mathrm{d}} = 0$ and $Z_{\mathrm{s}}=0$ are assumed, which corresponds to low-frequency measurement conditions, and leads to
\begin{align*}
&C_{\mathrm{dg,on,p}} |_{Z_{\mathrm{d}}=Z_{\mathrm{s}}=0} \\
&\qquad \qquad \approx \frac{C_{\mathrm{g^{\prime }}}R_\text{ch}(R_\text{ch}+R_\text{drift}+g_\text{ch}R_\text{ch}R_\text{drift})}{(R_\text{drift}+R_\text{ch})^{2}} \tag{18}
\\
&C_{\mathrm{sg,on,p}} |_{Z_{\mathrm{d}}=Z_{\mathrm{s}}=0} \\
&\quad \approx C_\text{ov}+\frac{C_{\mathrm{g^{\prime }}}R_\text{drift}(R_\text{ch}+R_\text{drift}+g_\text{ch}R_\text{ch}R_\text{drift})}{(R_\text{drift}+R_\text{ch})^{2}}. \tag{19}
\end{align*}View Source
\begin{align*}
&C_{\mathrm{dg,on,p}} |_{Z_{\mathrm{d}}=Z_{\mathrm{s}}=0} \\
&\qquad \qquad \approx \frac{C_{\mathrm{g^{\prime }}}R_\text{ch}(R_\text{ch}+R_\text{drift}+g_\text{ch}R_\text{ch}R_\text{drift})}{(R_\text{drift}+R_\text{ch})^{2}} \tag{18}
\\
&C_{\mathrm{sg,on,p}} |_{Z_{\mathrm{d}}=Z_{\mathrm{s}}=0} \\
&\quad \approx C_\text{ov}+\frac{C_{\mathrm{g^{\prime }}}R_\text{drift}(R_\text{ch}+R_\text{drift}+g_\text{ch}R_\text{ch}R_\text{drift})}{(R_\text{drift}+R_\text{ch})^{2}}. \tag{19}
\end{align*}
It was mentioned in Section III-C that the parallel-equivalent capacitance $C_{\mathrm{p}}$ is not affected by $i_{\mathrm{g_{ch}}} = g_\text{ch}v_\text{gs}$. Even though (18) and (19) depend on $g_\text{ch}$, the term $g_\text{ch}R_\text{ch}R_\text{drift} \ll (R_\text{ch}+R_\text{drift})$ for $g_\text{ch} \ll 1$. Thus, $g_\text{ch}R_\text{ch}R_\text{drift}$ can be neglected in (18) and (19) for very small values of $V_\text{ds}$. For $Z_{\mathrm{d}}$, $Z_{\mathrm{s}} \ne 0$, and $g_\text{ch}=$ 0 S, analytical solutions for $C_{\mathrm{dg,on,s}}$ and $C_{\mathrm{dg,on,s}}$ exist similarly to (16)–(17), which are not explicitly mentioned here for the sake of brevity. In contrast to (18)–(19), which are derived using the parallel equivalent model $C_{\mathrm{p}}$, no analytical solution can be found when using Assumptions 1–3 and approximation A2 ($g_\text{ch}\ne$ 0 S) for the series-equivalent model $C_{\mathrm{s}}$ (6). In this case, the deviations in $\varphi (Z_\text{dg})$ and $\varphi (Z_\text{sg})$ increase with decreasing frequency. Both $C_{\mathrm{dg,on,s}}$ and $C_{\mathrm{sg,on,s}}$ diverge to infinity for the frequency $f$ approaching zero ($C_{\mathrm{s}} \sim g_\text{ch}/f$). In consequence, the interterminal capacitances $C_\text{dg}$ and $C_\text{sg}$ must be extracted by the parallel equivalent model $C_{\mathrm{p}}$.
Equations (16)–(19) can further be simplified assuming $|Z_{\mathrm{d}}|$, $|Z_{\mathrm{s}}| \ll R_\text{ch}$, $R_\text{drift}$, and $i_{\mathrm{g_{ch}}} \ll i_{\mathrm{d}}$, $i_{\mathrm{s}}$ into
\begin{equation*}
C_{\mathrm{dg,on}}|_{|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}|\ll R_\text{ch}, R_\text{drift}; g_\text{ch}=0}=\frac{C_{\mathrm{g^{\prime }}}R_\text{ch}}{R_\text{ch}+R_\text{drift}} \tag{20}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{dg,on}}|_{|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}|\ll R_\text{ch}, R_\text{drift}; g_\text{ch}=0}=\frac{C_{\mathrm{g^{\prime }}}R_\text{ch}}{R_\text{ch}+R_\text{drift}} \tag{20}
\end{equation*}
and
\begin{equation*}
C_{\mathrm{sg,on}}|_{|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}|\ll R_\text{ch}, R_\text{drift};g_\text{ch}=0}=\frac{C_{\mathrm{g^{\prime }}}R_\text{drift}}{R_\text{ch}+R_\text{drift}}+C_\text{ov}. \tag{21}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{sg,on}}|_{|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}|\ll R_\text{ch}, R_\text{drift};g_\text{ch}=0}=\frac{C_{\mathrm{g^{\prime }}}R_\text{drift}}{R_\text{ch}+R_\text{drift}}+C_\text{ov}. \tag{21}
\end{equation*}
From (20) and (21) and the assumptions taken above, the ratio of $C_{\mathrm{dg,on}}/(C_{\mathrm{sg,on}}-C_\text{ov})$ can be expressed as
\begin{equation*}
\frac{C_{\mathrm{dg,on}}}{C_{\mathrm{sg,on}}-C_\text{ov}}=\frac{i_{\mathrm{d}}}{i_\text{ch}}=\frac{R_\text{ch}}{R_\text{drift}}. \tag{22}
\end{equation*}View Source
\begin{equation*}
\frac{C_{\mathrm{dg,on}}}{C_{\mathrm{sg,on}}-C_\text{ov}}=\frac{i_{\mathrm{d}}}{i_\text{ch}}=\frac{R_\text{ch}}{R_\text{drift}}. \tag{22}
\end{equation*}
B. Extraction of $R_\text{ch}$ and $R_\text{drift}$ From $C_\text{dg}$ and $C_\text{sg}$
The ratio of $R_\text{ch}$ to $R_\text{drift}$ can be calculated based on (22) from the values of the mosfet’s $C_\text{dg}$ and $C_\text{sg}$ characteristics, which are shown in Figs. 14 and 15. To solve (22) for $R_\text{ch}$ and $R_\text{drift}$, the value of $C_\text{ov}$ is approximated at the minimum of $C_\text{sg}$ by
\begin{equation*}
C_\text{ov}\approx \text{min}(C_\text{sg}). \tag{23}
\end{equation*}View Source
\begin{equation*}
C_\text{ov}\approx \text{min}(C_\text{sg}). \tag{23}
\end{equation*}
The approximation (23) is based on the assumption that in the mosfet’s off-state $C_\text{sg}=C_\text{ov}||(C_\text{g1}-C_\text{ch})$, as shown in Fig. 2(a) and (b). In depletion of the channel region, $C_\text{ch}$ becomes minimal and, thus, the capacitance of the series connection $C_\text{g1}-C_\text{ch} \approx C_\text{ch} \ll C_\text{ov}$. Hence, in depletion, $C_\text{sg}=C_\text{ov}||(C_\text{g1}-C_\text{ch}) \approx C_\text{ov}$. Although the estimation (23) is not precise, it is a good approximation which can be obtained solely from measured $C_\text{sg}(V_\text{gs})$. The estimated $C_\text{ov}$ and the corresponding $V_\text{gs}$ values of each DUT are listed in Table II. From (10) and (23), it follows that in strong inversion
\begin{equation*}
C_{\mathrm{sg,^{\prime }on}} = C_\text{sg}-\text{min}(C_\text{sg}) \approx C_\text{sg}-C_\text{ov}. \tag{24}
\end{equation*}View Source
\begin{equation*}
C_{\mathrm{sg,^{\prime }on}} = C_\text{sg}-\text{min}(C_\text{sg}) \approx C_\text{sg}-C_\text{ov}. \tag{24}
\end{equation*}
Based on the definition of the drain–source resistance
\begin{equation*}
R_\text{ds}=R_\text{ch}+R_\text{drift} \tag{25}
\end{equation*}View Source
\begin{equation*}
R_\text{ds}=R_\text{ch}+R_\text{drift} \tag{25}
\end{equation*}
and together with (3), (22), and (24), the following expression can be derived for $V_\text{gs}\gg V_\text{th}$:
\begin{equation*}
\frac{C_\text{gg}-\text{min}(C_\text{sg})}{R_\text{ds}} \approx \frac{C_{\mathrm{sg,^{\prime }on}}}{R_\text{drift}} \approx \frac{C_{\mathrm{dg,on}}}{R_\text{ch}}. \tag{26}
\end{equation*}View Source
\begin{equation*}
\frac{C_\text{gg}-\text{min}(C_\text{sg})}{R_\text{ds}} \approx \frac{C_{\mathrm{sg,^{\prime }on}}}{R_\text{drift}} \approx \frac{C_{\mathrm{dg,on}}}{R_\text{ch}}. \tag{26}
\end{equation*}
$C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}}$ is plotted for $V_\text{gs} >$ 0 V in Fig. 16 for all DUTs listed in Table I. When $V_\text{gs}$ is reduced below $V_\text{th}$ toward depletion, the values of $C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}}$ rapidly increase due to (23). The comparison of $C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}}$ at higher $V_\text{gs}$, e.g., at 20 V, shows the difference between SiC and Si power mosfets. For M1 and M2, $C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}} =$ {0.73, 0.96}, respectively, which is comparable to the simulation results presented in [41]. $C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}}$ of M3 (0.15) and M4 (0.006) are much lower, which means that their $R_{\mathrm{ds,on}}$ is mainly determined by $R_\text{drift}$. Overall, thes data demonstrate that SiC power mosfets have a thinner active device (epitaxial) layer, and thus, achieve a much smaller $R_{\mathrm{ds,on}}$ compared to Si power mosfets rated for the same nominal $V_\text{ds}$ blocking capability of, e.g., 1.2 kV, but also that the channel region of the SiC should be further optimized.
Fig. 17(a) shows the output characteristic ($I_{\mathrm{d}}-V_\text{ds}$) of M1 for $V_\text{gs}=$ {10, 14, 20} V, and Fig. 17(b) $R_{\mathrm{ds,on}}$ at $V_\text{gs} =$ 20 V. At $V_\text{ds}=$ 50 mV and $V_\text{gs} =$ 20 V, a drain current of $I_{\mathrm{d}}=$ 0.63 A is measured and $R_{\mathrm{ds,on}}=$ 0.079 $\Omega$ is calculated. Based on $C_{\mathrm{dg,on}}/C_{\mathrm{sg,^{\prime }on}}=$ 0.73 measured at $V_\text{gs} =$ 20 V, $V_\text{ds}=$ 0 V, a channel resistance $R_\text{ch}=$ 0.033 $\Omega$ and a drift resistance $R_\text{drift}=$ 0.046 $\Omega$ are calculated from (26); see Table II. The same approximation is valid for application relevant conditions of, e.g., $I_{\mathrm{d}}=$ 20 A, $V_\text{ds}=$ 1.75 V, and $R_{\mathrm{ds,on}}=$ 0.087 $\Omega$, as shown in Fig. 17, which results in values of $R_\text{ch}=$ 0.037 $\Omega$ and $R_\text{drift}=$ 0.05 $\Omega$.
SECTION VI.
Impact of Measurement Setup on the Measurement Accuracy
The influence of the measurement setup on the C–V extraction can be described by $Z_{\mathrm{d}}$ and $Z_{\mathrm{s}}$ of the DUT fixture as analytically derived in Section V-A.
To evaluate the impact of $Z_{\mathrm{d}}$ and $Z_{\mathrm{s}}$, the conditions $|Z_{\mathrm{d}}|=|Z_{\mathrm{s}}|\approx R_\text{ch}, R_\text{drift}$ are first addressed. The mosfet package terminals were extended with copper wires of a diameter of 0.4 mm and length of 11 or 40.5 cm, resulting in $|Z_\text{wire}| \approx |Z_{\mathrm{d}}| = |Z_{\mathrm{s}}|$ and $\varphi (Z_\text{wire})$ $\simeq$ $\varphi (Z_{\mathrm{d}}) \approx \varphi (Z_{\mathrm{s}})$. The changes in measured values of $C_\text{dg}$ and $C_\text{sg}$ are listed in Table III. The relative differences to using the fixture 16047E alone (see Fig. 3), are indicated by $e_{\mathrm{r}}$.
Next, the case $|Z_{\mathrm{d}}| \ne |Z_{\mathrm{s}}| \approx R_\text{ch}, R_\text{drift}$ is considered. For the measurement of $C_\text{sg}$, the same copper wire with a length of 40.5 cm (cf. Table III) was inserted only between the drain terminal and ACG ($|Z_\text{ACG}|\approx |Z_\text{wire}|\gg |Z_{\mathrm{s}}|$), cf. Fig. 6(b), whereas the source terminal was directly connected to AC$^\mathrm{-}$ of the fixture 16047E. For the measurement of $C_\text{dg}$, the source terminal was connected to ACG by the copper wire ($|Z_\text{ACG}|\approx |Z_\text{wire}|\gg |Z_{\mathrm{d}}|$) and the drain terminal directly to AC$^\mathrm{-}$. As a consequence of $|Z_\text{ACG}| \gg |Z_{\mathrm{AC^-}}|$, $C_\text{dg}$ and $C_\text{sg}$ increase 179 % and 16 % at $V_\text{gs}=$ 20 V. This effect of nonsmall $|Z_\text{ACG}| \ne |Z_{\mathrm{AC^-}}|$ is shown in Fig. 18 by the C–V results marked as nonsmall $|Z_{\mathrm{d}}|\ne |Z_{\mathrm{s}}|$.
From (16) and (17) and the results in Table III, it can be concluded that if a test fixture has nonsymmetric impedances, e.g., $|Z_{\mathrm{d}}| > |Z_{\mathrm{s}}|$ marked in Fig. 4, the division of $i_{\mathrm{g^{\prime }}}$ leads to $i_{\mathrm{d}} < i_{\mathrm{s}}$, which in turn leads to a measured $C_\text{sg}$ higher than a measured $C_\text{dg}$. Similarly, the same holds for $|Z_{\mathrm{s}}| > |Z_{\mathrm{d}}|$. In the case of $|Z_\text{ACG}| \gg |Z_{\mathrm{AC^-}}|$, $R_\text{ch}, R_\text{drift}$, the values of $C_\text{sg}$ and $C_\text{dg}$ converge both to the value of $C_\text{gg}$, since $-i_{\mathrm{s}}$ = $i_{\mathrm{g}}$ for the configuration of $C_\text{sg}$ and $-i_{\mathrm{d}}$ = $i_{\mathrm{g}}$ for the configuration of $C_\text{dg}$ measurements. Thus, for a strongly unequal $|Z_\text{ACG}| \gg |Z_{\mathrm{AC^-}}|$, $R_\text{ch}, R_\text{drift}$, the measurements lead to ($C_\text{dg}+C_\text{sg}) =$ 2 $C_\text{gg}$. If $|Z_{\mathrm{d}}| \approx |Z_{\mathrm{s}}| \gg R_\text{ch}, R_\text{drift}$, then $Z_{\mathrm{d}}$ and $Z_{\mathrm{s}}$ dominate in (16), (17) and cause an equal division of $C_\text{gg}$ into $C_\text{dg}=C_\text{sg}=$ 0.5 $C_\text{gg}$. This is typically the case in measurement setups which use longer cable extensions due to$|Z_\text{cable}| \gg R_\text{ch}, R_\text{drift}$.
Ideally, the magnitudes of $|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}|$ must be as small as possible, i.e., $|Z_{\mathrm{d}}| \approx |Z_{\mathrm{s}}| \ll R_\text{ch}, R_\text{drift}$. The influence of $wL_{\mathrm{d}}$ and $wL_{\mathrm{s}}$ of the drain and source package reactances is considered small at low frequencies such as 30 kHz. Accordingly, the disagreement of the gate capacitance characteristics with the relation (3) observed in [4], [12]–[16] can be ascribed to improper DUT connections, i.e., leaving the drain or source terminal floating, or high impedances $|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}| \gg R_\text{ch}, R_\text{drift}$ of the DUT fixture.
To verify the accuracy of C–V measurements, the extracted $C_\text{sg}$ can be compared for the bias conditions in accumulation, e.g., at $V_\text{gs}=$ $-$10 V, and in inversion, e.g., $V_\text{gs}=$ 20 V. In accumulation, $C_\text{sg} \approx C_\text{gg}$, but in inversion, $C_\text{sg}$ is typically smaller than $C_\text{gg}$ for SiC power mosfets (M1, M2), as it can be observed in Fig. 14. On the other hand, in the case of Si power mosfets (M3, M4), in inversion $C_\text{sg} \approx C_\text{gg}$, which can be related to a relatively large $R_\text{drift}$ and correspond to the small extracted ratios $R_\text{ch}/R_\text{drift} \approx$ 0.15, 0.006 (21).
The impact of $Z_{\mathrm{d}}$ and $Z_{\mathrm{s}}$ imposes criteria for selecting a measurement instrument. The measurement setup must provide a possibility to equivalently connect the 3- or 4-pins of the DUT, such that $|Z_{\mathrm{d}}|,|Z_{\mathrm{s}}| \ll R_\text{ch}, R_\text{drift}$. In addition, the instrument’s ampere meter must not add to $Z_{\mathrm{d}}$ or $Z_{\mathrm{s}}$.
The selection of the Keysight E4990A in combination with the test fixture 16047E provides a setup for minimal stray impedances $Z_{\mathrm{d}}$ and $Z_{\mathrm{s}}$, which can almost be limited to the parasitic inductances of the mosfet package. In comparison, direct RF-IV impedance analyzers such as the Keysight E4991B are not recommended for measurements of $C_\text{dg}$ or $C_\text{sg}$ since the condition $|Z_{\mathrm{d}}|, |Z_{\mathrm{s}}| \ll R_\text{ch}, R_\text{drift}$ cannot be achieved. A similar challenge arises when using network analyzers due to the characteristic impedance and impedance matching of the transmission line to typically 50 $\Omega$, as shown in [13], which requires correct de-embedding. Finally, when using on-wafer gate capacitance measurements of MOS transistors, the impedances of the coaxial cables severely influence the current divider of $i_{\mathrm{d}}/i_{\mathrm{s}}$ during the mosfet’s on-state.
The use of parametric curve tracers such as the Keithley 2600-PCT-4B [42] in combination with the impedance measurement unit Keithley 4210-CVU [43] or the Keysight B1505A, including the B1520A MFCMU [44], requires the use of external bias-Ts [10], [30], which distort the extracted capacitance values.
It should be noted that the deviation of $\varphi (Z_\text{dg})$ and $\varphi (Z_\text{sg})$ from −90 degree, shown in Section III-C, is insignificant if the lumped equivalent mosfet gate capacitances are extracted from $C_\text{gd}$ and $C_\text{gs}$ measurements. In reverse polarity of $v_\text{ac}$, i.e., by connecting the gate to AC$^\mathrm{-}$ and drain/source on either AC$^\mathrm{+}$/ACG, the mosfet’s reverse transconductance ($\partial i_{\mathrm{g}}/\partial v_\text{sg}|_{V_\text{ds}}$) is negligible. This was confirmed by using a Keithley 4210-CVU [43] with a Keysight 16047E test fixture, which allows to apply a reverse polarity of the $v_\text{ac}$ without changing the DC bias polarity. The Keithley 4210-CVU is a capacitance voltage unit, based on the autobalancing bridge measurement technique similar to Keysight E4990A, however, operating in a narrower frequency range from 1 kHz to 10 MHz.
This article reviews the requirements and specifies the conditions for accurate characterization of the interterminal gate capacitances of power mosfets, which is highly useful for device design optimization and accurate parametrization of device compact models. A measurement method for extracting the ratio $R_\text{ch}$/$R_\text{drift}$ of power mosfets is proposed, which can be used to increase the knowledge on the design of COTS discrete SiC power mosfets. The main conclusions are summarized in the following. 1) Capacitance measurements of packaged power mosfets should not predominantly be performed at 1 MHz, as typically specified in datasheets, but rather at lower frequencies in the order of some 10 kHz to minimize the influence of the parasitic effects.
2) The influence of the mosfet’s transconductance leads to a deviation in $\varphi (Z_\text{dg})$ and $\varphi (Z_\text{sg})$ for $V_\text{gs} \geq V_\text{th}$, which results in distorted capacitance values when extracted by the series-equivalent model $C_{\mathrm{s}}$. Therefore, the lumped equivalent capacitances of the mosfet should be modeled by the parallel equivalent capacitance model $C_{\mathrm{p}}$ when extracted from measured $Z_\text{dg}$ and $Z_\text{sg}$ characteristics.
3) The contributions of $R_\text{ch}$ and $R_\text{drift}$ to the overall $R_{\mathrm{ds,on}}$ of power mosfets can be directly derived for any 3- and 4-pin device from the values of the mosfet’s $C_\text{dg}$ and $C_\text{sg}$ characteristics.
4) The measurement accuracy can significantly be hampered by the impedance of the measurement setup, i.e., unsuitable connection of the DUT or the test fixture. Consequently, only specific standard measurement instruments employing an autobalancing bridge measurement technique are recommended for characterization of interterminal gate capacitances of MOS transistors.
The presented analysis represents a valuable input toward standard guidelines on the C–V characterization of power mosfets.