Synapse and Tunable Leaky-Integrate Neuron Functions Enabled by Oxide Trapping Dynamics in a Single Logic Transistor

We show that a high-k gated n-MOSFET can embody both the memory plasticity of a synapse and leaky-integration of a neuron, by virtue of the rich temporal dynamics of charge capture/emission by gate-oxide defects. In addition, a tunable leaky-integrate function is demonstrated. The lower limit of energy per input spike is on the order of fJ, which provides room for low-power trigger circuit design and scalability. This work points to the prospect of a gate-engineered logic transistor serving as the universal building block of hardware spiking neural networks, thereby accelerating the realization of compact, energy efficient neuromorphic computers given the relative maturity of the transistor technology.

I. Introduction

To overcome the von Neumann bottleneck, single artificial synapse and neuron that enable space and energy efficient implementation of hardware spiking neural networks are desired. Although work involving the floating-gate transistor began as early as the 1990s [1], progress was limited by structural and voltage incompatibility with logic devices. Following the demonstration of memristor function in late 2000s [2], interest gravitated towards memristive devices due to their simple structure and analog memory characteristic [3]–[6]. In a memristor crossbar array, however, select devices (typically transistors) are needed for suppressing the well-known sneak-path current [7], [8]. Integration complexity, coupled with inherent device variability problem have shifted the attention to memtransistors, which offer analog memory and self-select functionality. Among the memtransistors explored [9], hafnia-based ferroelectric FETs appear promising due to silicon process compatibility [10]–[13]. However, key challenges remain, which include high operating voltage, limited stack thickness (hence voltage) scaling, and influence of interface/oxide charge trapping on device operation [14].