A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology

In this article, a CMOS Ku -band phased-array transmitter with eight elements is demonstrated. To mitigate the measurement time and complexity, a built-in self-test (BIST) circuit is developed in this chip. A fully symmetrical sampling structure is proposed to improve the testing accuracy of the BIST system. To decrease the phase and amplitude errors, two compensation methods based on inductors and capacitors are, respectively, used in the phase shifters and attenuators to minimize severe parasitic effects of transistors in high-frequency bands. In addition, a scalable power divider is developed to save chip area and reduce insertion loss. According to the measurement results, the 5-bit passive phase shifter in each transmitting channel achieves less than 3.6° root-mean-square phase error (RMSPE) and 0.8-dB root-mean-square amplitude error (RMSAE). The transmitter’s attenuators are formed by four bridge- $T/\pi $ -type units and achieve less than 0.94-dB RMSAE and RMSPE of 3.2°. Each channel of the transmitter is capable of delivering about 13-dBm linear power at 16 GHz. The BIST system is also employed to detect the phase and amplitude performances of the eight-element transmitter, and the BIST testing errors are less than 10.3% compared to the microwave equipment measurement.

I. Introduction

Phase-array systems have been widely researched and applied in radar systems to replace conventional mechanical waveform scanning architectures because the electronic waveform controlling can sweep at an extremely faster speed than mechanical approaches. In addition, the phased-array technique can significantly increase the effective isotropic radiated power (EIRP) of the transmitter chain and signal-to-noise ratio (SNR) of the receiver chain [1], [2]. Due to these characteristics, phased-array systems and related multichannel transceiver chips have attracted wide attention from the industrial and academic fields in recent years. Advanced CMOS processes featuring high integration and reliability have demonstrated their remarkable advantages in high-frequency large-scale phased-array transceiver chips design [3]. The literature [4] reports a -band CMOS phased-array transceiver front end that integrates a number of the element up to 256 in a single chip and hence attains a considerable EIRP of 38.5 dBm. However, large-scale phased-array transceiver chips pose critical challenges in characteristic measurement and calibration of phase and amplitude [5].