I. Introduction
The increase in the complexity of the VLSI chips, and the decrease in the feature size of the chips demand larger grids for power distribution. This causes the design and verification of the power networks have become a challenging task. The inferior designed power distribution network can degrade the circuit performance, noise margin, and the reliability. Since the power grids are rapidly becoming a limiting factor in high performance microprocessors, the ability of analyzing power grids efficiently is a critical requirement to obtain a robust design [1], [2], [3], [4], [5].