Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

A compute SRAM requires high speed for both compute access and normal read access. However, it presents a very distinct bitline discharging behavior in these two modes, thus brings a significant challenge to the design of its sensing amplifiers. State-of-the-art sensing amplifiers, namely the symmetric single-ended sensing amplifier (SS-SA) and the asymmetric differential sensing amplifier (AD-SA), cannot support a high-speed compute access and normal read access at the same time. To solve this problem, first, we perform a comprehensive analysis of these two sensing topologies and find that AD-SA requires a smaller bitline voltage difference than that of SS-SA, but it is still relatively large. This guides us to design an improved AD-SA for high-speed compute access. Second, we propose a novel reconfigurable sensing amplifier (R-SA) that can dynamically reconfigure its circuits in a compute access or in normal read access, to optimize its access delay in both modes. Compared to the state-of-the-art, results show that our R-SA has reduced the access delay by 17% and 45% for compute access and normal access, respectively, in an 8 Kb compute SRAM using a 55 nm CMOS technology. In addition, the proposed R-SA also saves the access energy by 9%.

I. Introduction

In-SRAM computing has been widely explored to mitigate the memory wall constraints in the von-Neumann computer architecture [1], [2]. A compute SRAM (CSRAM) exploits a technique called “bitline computing” [3], which simultaneously accesses two rows of bitcells sharing the same pair of bitlines so that some logic/arithmetic functions can be achieved by sensing the bitline voltages [4]–[6]. This compute SRAM presents quite distinctive bitline discharge behaviors compared to a normal SRAM. For example, the bitlines of CSRAM will generate three different voltage levels during compute access. Besides, the CSRAM also needs to maintain the normal SRAM function (i.e., a normal read access) [7], [8]. However, it is challenging to design high-speed sensing topologies that are optimized for both compute access and normal read access [9], [10].