Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance.

I. Introduction

Ring voltage-controlled oscillator (RVCO)-based clock generators have been gaining more interest in recent years for different implementations due to their superiorities of wide frequency tuning range, compact silicon area, and the freedom from magnetic coupling compared with their LC-oscillator-based counterparts. However, RVCO intrinsically suffers from poor phase noise (PN), making it hard to achieve a low-jitter clock with low power consumption. Therefore, the jitter suppression technique is preferred for the RVCO to compensate for the PN performance gap compared with the LC-type [1]. Conventionally, VCO PN is high-pass filtered via the phase-locked loop (PLL) with an effective strength limited by its loop bandwidth (BW). For a conventional type-II PLL, the loop BW is less than a tenth of the reference frequency () to ensure the loop stability. Yet, it is still not large enough to reduce the poor RVCO PN. To overcome this BW limitation, promising techniques like injection-locked clock multiplier (ILCM) and multiplying delay-locked loop (MDLL) are considered to be an alternative solution that the jitter accumulation within the VCO is reset periodically by the reference clock [2].