Introduction
Multi-level inverter (MLI) technology is developing quickly due to several advantages over conventional two-level inverters. These topologies are capable of generating low voltage total harmonic distortion (THD) by increasing the number of voltage levels. Furthermore, MLI topologies reduce the voltage rating of power switches by sharing the DC link voltage on power switches, and they can operate at low switching frequencies for a given output waveform quality. As a result, MIL can be used in grid-connected applications such as Photovoltaic (PV) Systems, Wind, Fuel Cell, Flexible Alternating Current Transmission System (FACTS) devices, and Electrical Vehicles (EV) [1]–[4]. The basic operation principles of MLIs can be found in the neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) configurations [5]–[7].
The cascaded MLI configurations in the literature have been presented in three categories: switched DC source multilevel inverters (SDC-MLIs), switched-diode multilevel inverters (SD-MLIs), and switched capacitor multilevel inverters (SC-MLIs). The SDC-MLIs use multiple independent DC voltage sources, the SD-MLIs use lots of discrete diodes which are replaced by switches and SC-MLIs use several capacitors with one DC source to reduce the number of power switches [8]–[11]. In this article, the focus is on the presented topologies of SDC-MLIs, with the weaknesses and strengths being discussed in the following. To achieve a large number of voltage levels, all types of multilevel inverters and their cascaded topologies require a high number of components which causes some technical issues, such as: increasing the final system cost, increasing the probability of device failure, and requiring a switch to each driver circuit. To overcome these issues, there has been carried out the design of alternative MLI configurations [8]–[11]. These configurations lead to a reduction in the active component count over conventional cascaded MLI configurations. Several reduced single-phase SDC-MLI configurations have been published in the literature [12]–[16]. An improved configuration of the modified T-type inverter has been presented by Samadaei et. al. in [12], which generates seventeen-levels in asymmetrical mode with a reduced number of switches in the symmetrical pattern in comparison with other MLIs. The benefit of this topology is, low voltage stress because using bidirectional power switches. Despite the fact that this MLI generates a large number of levels (17), the number of power switches, driver circuits and DC sources remains high. The presented structure by Samadaei et. al. [13] is an advanced topology [12] called a K-type inverter. The K-type MLI generates 13 voltage levels with 14 switches, 11 drivers, 2 unequal DC sources and 2 capacitors. This topology aimed to reduce the amount of DC power supplies by replacing two capacitors with two DC power supplies. The drawback of this topology is a high number of components (IGBTs, drivers) when a large number of levels are needed. Furthermore, the number of On-switches is high, resulting in high conduction losses. In [14], Alishah et. al. have recommended a topology based on a developed H-bridge module for general multilevel inverter topologies. The benefit of this MLI is a reduction in the number of components as well as reduced voltage stress of the switches. The topology presented in [14] is a general topology that can operate in both symmetric and asymmetric modes. The benefit of this topology is the use of bidirectional switches to reduce voltage stress, but it still requires a large number of DC sources and components when a large number of levels are required. In [15] by Sathik et. al., a reduced generalized multilevel converter topology has been presented based on a basic unit which is able to develop as two states (extended basic unit and cascade connection) to decrease blocking voltage and components. The given basic unit of this topology is an asymmetric structure and uses 10 unidirectional power switches and 4 DC power supplies to generate 9-level. Using 10 switches to produce 9 levels is a large number of switches that results in the need for a complex modulation technique. In [16], by Sathik et. al. A SDC-MLI structure has been presented with the same circuit as in [15]. This topology was developed for the asymmetric topology to increase the number of voltage levels from 9-level to 17-level using the same components. This topology uses two unidirectional switches instead of one bidirectional switch to reduce the voltage stress. Although this MLI decreases the voltage stress, it requires a high quantity of components to produce high voltage levels.
In addition to the discussed above MLIs, recently, new multilevel inverters have been presented based on different objectives: reduced switches count, reduced DC sources, the reduced voltage stress on power switches, etc.) [17]–[21]. In [17]–[21], five different 15-level reduced MLI configurations have been reported. Siddique et al.’s presented reduced MLI topology in [17] that handles ten power switches to switch three DC sources to make fifteen-voltage levels. The drawback of this topology is using a high number of switches. A modular topology for symmetric MLI configurations has been presented by Nasiri et. al. in [18]. It uses ten switches (bidirectional and unidirectional) and seven DC sources to make 15-level. The disadvantage of this topology is the large number of DC sources; in a real application each DC source requires a capacitor which increases the system’s power loss. A modified packed U-cell multilevel inverter has been presented by Hosseinzadeh et. al. in [19] which reduced the number of switches to generate fifteen voltage levels. The drawback of this topology is that it cannot handle the back-flow current due to the use of diodes in its circuit. Presented topology by Majumdar et. al. in [20] combines a classical five-level T-type inverter with a three-level H-bridge inverter to reduce voltage stress on the switches. It requires nine power switches with four extra diodes. A cascaded multilevel inverter topology based on an extendable basic unit has been developed by C. Dhanamjayulu et. al. in [21]. This multilevel inverter is a symmetric topology that uses an H-bridge converter to change the polarity of the output voltage. The H-bridge inverter that is used should endorse the maximum output voltage magnitude that leads to an increase in the power losses and cost of the inverter. Using two basic units of this topology, with 16 power switches and 7 DC sources, it can produce 15-level. Therefore, this MLI requires a high number of components making it less efficient and unaffordable.
Regarding switched capacitor MLIs, a new K-type MLI has been reported by Zeng et. al in [22]. This topology handles one DC source and four capacitors with ten power switches to generate 13-level. The benefit of this MLI is the self-balancing of the capacitor’s voltages; it still needs a high number of switching devices. Bana et. al have introduced two hybrid MLI configurations in [23]. These hybrid MLIs can make 13-level and 19-level with nine and eleven power switches with six DC-sources and one capacitor, respectively. Khan et. al have developed a symmetric step-up switch capacitor MLI in [24] that creates 2n+1 voltage levels. The benefit of this MLI is the self-balancing of capacitors and using one DC source; in contrast, it uses a high number of power switches and capacitors to generate a high number of levels.
This article aims to propose a new symmetric and asymmetric switched DC source MLI using fewer switching devices and gate drivers making the control system of the proposed topology simpler. The different arrangements of DC power supplies are presented for the extended cascaded topologies. The comparison studies are performed in terms of the number of elements (switches, drivers, diodes), isolated DC power supplies, and total blocking voltages. The power loss analysis of the proposed topology, the grid-connected PV application, and selection of power switch voltage rating are discussed. Finally, simulation and experimental results are presented to validate the proposal.
Principle Operation of the Proposed Sub-Module Topology
A. Circuit Description
Fig. 1(a) indicates the power circuit of the proposed sub-module topology. As can be seen from this figure, the numbers of switches and DC power supplies in the proposed topology are eight and four, respectively. The type of power switches
B. Operation Modes
The proposed topology has various operating modes that are generated by the activation of the different switching devices. Fig. 1(b) shows the operation modes for the proposed sub-module topology (corresponding to Table 1). Table 1 gives the synthesis of the state of the switches to generate each level, where the 16 switching states are shown by the different on and off switches. As can be seen in Table 1, there is one redundancy for making zero levels. Some of the operation modes of the proposed topology are explained as follows:
There are two states for generating zero levels in the first mode, so switches
The second mode is for generating
In the sixteenth mode for generating the maximum voltage level in positive and negative
Dependent on the choosing magnitudes of DC power supplies, the proposed topology can generate different voltage levels, however, the sub-module topology creates seven voltage levels in symmetric mode by considering the same magnitudes of DC power supplies of (
C. Total Blocking Voltage
The maximum total blocking voltage (TBV) is an essential factor in the design of multilevel inverter topologies. The maximum TBV in the proposed sub-module topology is the sum of the blocking voltages in which the power switches suffer. The maximum TBV of the proposed sub-module topology is obtained as follows:\begin{equation*} TBV_{sub}=V_{S1}+V_{S2}+\ldots +V_{S8}\tag{1}\end{equation*}
The magnitude of the maximum blocking voltage on each switch is:\begin{align*} V_{S1}=&V_{S2}=V_{2}\tag{2}\\ V_{S3}=&V_{1}+V_{2}+V_{4}\tag{3}\\ V_{S4}=&2V_{1}+V_{2}+V_{4}\tag{4}\\ V_{S5}=&V_{S6}=V_{3}\tag{5}\\ V_{S7}=&V_{1}+V_{2}+V_{3}\tag{6}\\ V_{S8}=&2V_{1}+V_{2}+V_{3}\tag{7}\end{align*}
According to the magnitudes of the maximum blocking voltage by each switch, the value of the maximum TBV for the proposed sub-module topology is obtained as:\begin{equation*} TBV_{sub}=\sum _{i=1}^{8}V_{Si}=6(V_{1}+V_{2}+V_{3})\tag{8}\end{equation*}
The value of TBV can be rewritten according to the number of levels of the proposed sub-module topology as follows:\begin{equation*} TBV_{sub}=3(N_{level}-1)\tag{9}\end{equation*}
Extended Cascaded Configurations
A cascaded topology is the connection of an \begin{equation*} N_{L}=6n+1\tag{10}\end{equation*}
Here
In an asymmetric cascaded topology, the magnitudes of all DC supplies are different. Depending on the choosen methods of determination of DC supplies, the proposed cascaded topology generates different voltage levels. Table 3 gives the proposed arrangements for the magnitudes of DC supplies. In this Table the recommended quantities of DC supplies arrange from the minimum number to the maximum number of voltage levels, which the suggested cascaded topology can create. For example, if two asymmetric sub-module topologies are connected as cascades, the total number of levels is 29-level (
The proposed sub-module topology, CHB, and presented MLI topologies in, [12]–[16], requires several independent DC power supplies in the input. There are different methods for supplying the input DC sources of the proposed topology, some of which are illustrated in Fig. 3. Two regulation DC-link systems have been presented for the first time in [25], [26] to generate distinct DC voltage source magnitudes. It is worth mentioning, the improved regulated DC-link Fig. 3(a) was resented in [30] and was suggested for a medium voltage DC link. The presented first system (Fig. 3(a)) comprises an AC voltage source which can be a local power grid, a multi-tap transformer and a diode-bridge rectifier circuit along with DC capacitors that are usually used for motor drive applications. The second system (Fig. 3(b)) uses several independent DC/DC converters which are suitable for renewable energy applications such as wind, solar, fuel cell, etc.
DC-link regulation systems; (a) multi-tap transormer; (b) DC/DC converters; (c) multi-input multi-output buck converter; (d) multi-input multi-output boost converter.
The third and fourth systems (Figs. 3(c) and 3(d)) have been presented in [28], [29] which are multi-input and multi-output buck and boost converters which are also suitable for renewable energy applications. Hence, we recommend these systems (depending on the application) to regulate the input DC-link of the proposed topology. It should be noted that the objective of this article is to present a new sub-module topology for the multilevel inverter configurations, not a method to supply the DC-link voltage in the multilevel inverters.
Comparison Outcomes
To demonstrate the proposed topologies’ strengths and weaknesses, a comprehensive study was conducted among the proposed topologies, CHB, and other published MLIs [8] and [12]–[16]. The comparative study was performed in terms of the number of IGBTs, switches, discrete diodes, DC power supplies, capacitors, on-state switches, the variety of DC power supplies, and the magnitude of TBV to endorse the new capabilities of the proposed topologies in competition with other MLIs. Table 4 summarizes all parameters of proposed cascaded MLIs and other cascaded MLIs that are used for the comparison. The number of required IGBTs in each MLI for both symmetric and asymmetric DC sources to make the various numbers of voltage levels are represented in Fig. 4(a). As one can see in Fig. 4(a), the proposed topologies (M1 and M2) diminish the number of IGBTs compared to other MLIs to produce the same voltage levels. The number of required power switches (gate drivers) in each topology for both modes of symmetric and asymmetric to create different number levels are exhibited in Fig. 4(b). According to the figure, it is apparent that the proposed topologies use fewer power switches to create the maximum number of levels. The comparison of the number of power diodes versus the number of levels for all MLI topologies is shown in Fig. 4(c). As can be seen from this figure, the proposed topology requires a lower number of diodes than other topologies. Fig. 4(d) exhibits the required number of DC power supplies to generate different voltage levels in all presented MLI topologies. Concerning this figure, in the asymmetric mode, after CHB (R4, R5), and reported MLIs [14]–[16], the proposed topology (M2) requires a minimum number of DC power supplies to create the same voltage levels as other MLIs. The minimum value of the DC voltage source in the symmetric mode belongs to the presented MLI in [13].
Comparison studies for both asymmetric and symmetric cascaded topologies; (a) variation of
One of the factors that impact the cost of cascaded multilevel inverters is the variety of DC power supplies. This factor has been introduced in [8] for the first time. After that, it has been used in other publications for comparison.
Fig. 4(f) presents the variation of the maximum total blocking voltage versus the different levels in all topologies. According to this figure, in the symmetric and asymmetric modes, the proposed topology has a reduced (TBV) value and it has a low value close to four recent presented topologies [12] and [14]–[16].
Further, to the above comparison, the proposed asymmetric sub-module topology is compared with other MLIs in aspects of required component counts to make fifteen voltage levels. Noted, some MLIs cannot generate exactly 15-level, they can generate 13 and 17 levels that are close to 15-level. As depicted in Table 5, the proposed asymmetric inverter requires a lower number of switching devices and gate drivers than other MLIs.
Power Losses Calculations and Comparison
The power losses depend on switching losses and conduction losses [10], [12], [13]. The switching losses are dissipated power during switching turn-on and turn-off of the power. Losses are calculated for the switch and the anti-parallel diode, which is highly proportional to the switching frequency (\begin{align*} P_{s,on,n}=&\int _{0}^{t_{on}}v(t)i(t)dt \\=&\int _{0}^{t_{on}}\left [{\frac {I(t-t_{on})-v_{block,n}t}{t_{on}}}\right] dt \\=&\frac {1}{6}\times I\times t_{on}\times V_{block,n}\tag{11}\\ P_{s,off,n}=&\frac {1}{6}\times I\times t_{off}\times V_{block,n}\tag{12}\end{align*}
Here, \begin{equation*} P_{L,s,n}=f_{s}(P_{s,on,n}+P_{s,off,n})\tag{13}\end{equation*}
Here, \begin{equation*} P_{L,s,n}=\frac {2\times I\times t_{on}}{6}\times f_{s} \times V_{block,n}\tag{14}\end{equation*}
By considering \begin{equation*} P_{L,s,n}=c\times f_{s}\times V_{block,n}\tag{15}\end{equation*}
By replacing eqs. (2)–(7) in eq. (15), the switching losses for 15-level asymmetric sub-module topology \begin{align*} P_{L,s,asymmetric}=&c\times \big (f_{s}(V_{1}+4V_{2}+4V_{3}+V_{4}) \\&+2f_{o}(V_{1}+V_{2}+V_{3}+V_{4})\big)\tag{16}\end{align*}
Here, \begin{align*} P_{L,s,asymmetric}=&c\times V_{dc}\times (26f_{s}+16f_{o}) \\=&26\times c\times V_{dc}\times \left({f_{s}+\frac {16}{26}f_{o}}\right)\tag{17}\end{align*}
For the reason that \begin{equation*} P_{L,s,asymmetric}=26\times c\times V_{dc}\times f_{s}\tag{18}\end{equation*}
Similarly, by using eq. (15) the switching losses for a 15-level CHB converter is (
The conduction losses of multilevel inverters depend on the number of switches in which they are in an on-state mode in the current path at every time instance [12]–[14]. Therefore, the conduction losses are obtained by calculating the number of active devices in multilevel inverter topologies. For the proposed sub-module topology, the maximum number of on-state IGBT based on the switching table (see Table 1) is three.
The power loss of the proposed 15-level topology is seen in the PLECS environment. For this study, the IGBT IKFW40N65ES5 is chosen. The simulation results are obtained at 5[kW] output power. The input DC sources are assumed to be
Power loss study of proposed 15-level MLI topology; (a) switching and conduction losses of power switches and diodes; (b) temperature of the switches; (c) efficiency.
Recently, several PWM techniques have been presented for power converters in the literature, such as standard Sinusoidal PWM (S-PWM) and Space Vector PWM (SV-PWM), and advanced PWM methods such as Modified Total Harmonics Distortion PWM (MTHD-PWM), and Trapezoidal Total Harmonics Distortion PWM (TTHD-PWM), etc. [31]–[34]. The advanced PWM approaches present several advantages over the standard ones, such as low switching and conduction loss, which improve the efficacy of the converters. Hence, the power loss analysis of the proposed topology is presented by two aforementioned advanced PWM methods. Therefore, these PWM techniques are applied to the proposed 15-level converter to show their advantage over the proposed topology.
The power loss simulation for the presented PWM methods and standard SPWM is performed in the PLECS environment. A comparison is made between the advanced PWM techniques and the standard ones. Table 6 illustrates the power losses of the proposed converter which is mutilated by standard S-PWM, MTHD-PWM, and THTD-PWM. The power losses are calculated for different modulation indexes (0.8, 0.9, and 1.0) at a fixed switching frequency of 2[Khz]. As can see from this table, the conduction (
Application and Power Switches Selection Example
A. Grid-Connected PV Application of the Proposed Topology
The proposed topology is a general topology, the same as other topologies of multilevel inverters that can be applied to renewable energy sources (PV and Wind), EVs, FACTS, etc. As an example, the proposed topology can be applied to grid-connected PV applications due to requiring fewer power switches and drivers, which makes the system more efficient. Fig. 7 shows the application of the proposed topology in the grid-connected PV system. To regulate the grid current in a sinusoidal shape, an effective control technique is adopted which provides a near unity power factor with the grid voltage. To do this, the individual DC link voltages should be kept equal to their DC-link references (
Proposed Control scheme for grid-connected PV application of the proposed topology.
1) Total DC-Link Voltage Control
To inject a maximum current into the grid with a fixed nominal voltage by the proposed inverter, the output voltage of the inverter is controlled by a close-loop control, as shown in Fig. 7. The total DC-link voltage is controlled by comparing the DC-link voltage reference (
2) Grid Current Control
A Proportional Resonance (PR) current control method is utilized to control the grid current. The reference current is made by multiplying the output of PLL (
3) Individual DC-Link Voltage Control
In order to produce 15-level with the proposed inverter, the ratio of DC-link voltages is kept at a binary algorithm (1:2:4) under the environmental variations of PV panels. The overall DC-link voltage controller is controlled at the total DC link voltage of the inverter equal to
4) Proposed Phase-Shift Carrier Base PWM Modulation Technique
A Phase-Shift Carrier base Sinusoidal PWM (PSC-SPWM) modulation technique is proposed to generate switching pulses for the proposed grid-connected 15-level multilevel inverter. Fig. 8(a) shows the block diagram of the proposed PSC-PWM modulation method. To produce a 15-level, fourteen high-frequency triangular carriers with the same magnitude of −1 to +1 but with different phases are defined and compared with the modulation index (M) that has the frequency of grid voltage. As discussed above, the modulation index (M) is generated by the presented control system in Fig. 7. The amplitude of reference voltage (
Proposed PS-PWM modulation technique for the proposed 15-level topology; (a) modulation block diagram; (b) reference voltage, output waveform, carriers; (c) generated switching pulses of proposed topology based on PS-PWM.
B. Calculation of Power Switches for Medium-Voltage Applications
The selection of power switches in the proposed topology is related to the voltage rating of each switch. The maximum operating voltage (3-phase line–line RMS voltage) of the proposed topology is obtained by
Table 7 illustrates the commercial IGBT voltage rating for the proposed 15-level sub-module inverter and 225-level cascaded topology. According to Table 7, the maximum standing voltage is related to four switches (
Simulation Results of the Proposed Inverter for Grid-Connected PV Application
The simulation results of the proposed 15-level topology are conducted in MATLAB/Simulink software in a single-phase grid-connected PV system. The proposed topology is controlled based on the suggested control scheme, which is presented in section VI.
The PV sources are connected to the proposed topology through four independent DC-DC boost converters which are controlled by the P&O MPPT algorithm. The detail of single-phase PV panels, boost converters and output filter and grid parameters, are listed in Table 9. Fig. 9 shows the steady-state simulation results of the grid voltage (
Steady state simulation study; (a) grid voltage and grid current; (b) inverter voltage; (c) grid current and reference current; (d) PV voltages, DC-link voltages and reference DC-link voltages.
Voltage stress of switches; (a)
The proposed 15-level inverter is simulated and tested for different environmental conditions of PV sources. The results are shown in Fig. 11. As can be seen from Fig. 11(a), in the first the irradiance and temperatures of all four PV panels are set to 1000[W/
Simulation study for irradiance variations; (a) PV irradiance; (b) PV voltages, DC-link voltages and reference DC-link voltage; (c) inverter voltage; (d) grid current and reference current; (e) zoomed inverter voltage at decreasing irradiance from 1000 to 700[Kw/
In addition to the input variations, the response of the inverter to the output variations (
Simulation study for grid voltage variations; (a) grid voltage; (b) PV, DC-link and reference voltages; (c) inverter voltage; (d) grid and reference currents.
Experimental Validations
The simulation and experimental results for three topologies, symmetric 7-level, an asymmetric 15-level sub-module topology, and a 29-level cascaded topology are presented to validate the performance of the proposal. IGBTs are used as switching devices in the topology prototype. The list of components is used for experimental set-up is shown in Table 10. To control switching pulses of the proposed topology, the presented Fundamental Frequency Modulation (FFM) technique in [10] is applied to control of the proposed topologies because it is simple and easy to implement at a high number of levels. Additionally it uses low-frequency switching that causes low power losses. This modulation technique uses a sinusoidal stepped waveform with a fundamental frequency as illustrated in Fig. 13. In this technique, by considering the desired total number of levels \begin{equation*} \alpha _{j}=sin^{-1}\left({\frac {j-0.5}{N_{L}}}\right) \quad for j=1,2,\ldots,\frac {N_{L}-1}{2}\tag{19}\end{equation*}
Then, the switching angles generate the switching pulses of the proposed multilevel inverter which are determined separately based on the switching states in Table 1. The step timing is chosen based on the output frequency and is calculated offline.
The field-programmable gate array (FPGA) is used to generate pulses, to implement the presented fundamental frequency modulation technique for the proposed topologies. The 7-level, 15-level and 29-level switching states are programmed by Verilog-language in Xiling software. Then, the switching states transfer to Basys 2 hardware. 2[
A. Seven-Level Symmetric Evaluation
Fig. 14 is the prototype picture of the proposed sub-module inverter with eight power switches and four equal DC source magnitudes. The simulation and experimental results of the symmetric 7-level sub-module inverter are shown in Fig. 15. The magnitudes of all DC power supplies are set at 15[V]. The output voltage and current waveforms of the proposed 7-level sub-module topology in both simulation and experimental results are presented in Figs. 15(a) and 15(b) with a pure resistance load 60[
The prototype picture of the proposed sub-module and cascaded multilevel inverters.
Simulation and experimental results of symmetric 7-level proposed sub-module inverter; (a) simulation results of the output waveforms of proposed 7-level inverter with R-load; (b) experimental results of the output waveforms of the proposed 7-level inverter with R-load; (c) simulation results with R-L load; (d) experimental results with R-L load.
B. Fifteen-Level Asymmetric Evaluation
In asymmetric sub-module topology, four DC power supply magnitudes are set by a binary algorithm (1:2:4). The quantity of DC supplies required to create 15-level in the experimental study corresponds to
Simulation and experimental results of an asymmetric 15-level proposed sub-module inverter; (a) simulation results of the output waveforms with R-load; (b) simulation results with RL-load (c) zoomed view of the output waveforms in 2ms; (d) experimental results of the output waveforms with R-load; (e) experimental results with R-L load (f) zoom view of (f) in 2ms; (g) experimental output waveforms with R-L load; (h) experimental results of the load voltage and current waveforms with a step change load; (i) step change load zoom of the output and current waveforms.
The dynamic response of the proposed 15-level inverter is tested with a sudden load change, which is a typical test for single-phase multilevel inverters. The experimental results of dynamic response are presented in Fig. 16(h) and 16(i). The value of the load changes from a 60[
Experimental results blocking voltages on power switches and diodes of proposed 15-level sub-module inverter; (a) blocking voltages of power switches
In order to calculate the efficiency (
C. Twenty-Nine-Level Cascaded Topology
The experiment results of the proposed cascaded topology have been conducted—the proposed cascaded topology is comprised of two proposed asymmetric sub-module topologies. The proposed asymmetric inverter with two series sub-module inverters can make a maximum 225-level based on the proposed method (
Experimental results of proposed 29-level cascaded topology; (a) output voltage of first sub-module topology
Discussion
The performance of the proposed sub-module topology was validated through simulation and experimental analysis for both symmetric and asymmetric sources under resistance and resistance-inductance loads and in a grid-tied PV system. Corresponding to the presented performance analysis, the proposed topologies are able to generate all levels based on presented theoretical concepts and can also work in both operation modes as well as having good performance with a pure sinusoidal current waveform. Evaluation of the reliability of MLIs to apply in a real application is an essential function of their design. In this paper, the reliability of the proposed topology is discussed in terms of control complexity and the capability of creating a large number of levels.
A. Control Complexity
Classical topologies NPC, FC, as well as the presented topologies of [13] and [22]–[24] require several sensors (voltage/current), costly controller, signal processing circuits, and sophisticated control algorithm, to deal with the voltage balance of capacitors. These will introduce complexity and reduce reliability. Conversely, the proposed topology does not require any capacitor to balance the capacitor voltages. Indeed, it does not need any sensors or complicated control, which enhances the reliability of the proposed MLI than other MLIs that use capacitors in their circuits.
Conclusion
In this article, a reduced sub-module topology was proposed for cascaded multilevel power inverters with reduced switching devices to be applied to renewable energy sources. The presented sub-module topology generates seven voltage levels in symmetric sources and fifteen voltage levels in asymmetric sources with eight switching devices. A cascaded configuration with several DC source arrangements was investigated to minimize the number of switching devices, the number of gate drivers, and the cost of the inverter. The comparison outcomes indicate that the required switching devices for fifteen levels in the proposed sub-module topology have been reduced by thirty-three percent in contrast to the CHB multilevel inverter. The cost of the proposed fifteen-level sub-module topology was reduced compared to other recent multilevel inverters for medium voltage applications. In addition, in order to show flexibility and performance of the proposed topology in grid-tied PV applications, a close-loop control system was proposed in which the proposed inverter was modulated with high-frequency PSC-PWM. The obtained results from simulations and experimental validation have demonstrated that the proposed sub-module topology and its cascaded connection are able to operate in both symmetric and asymmetric sources with a reduced number of switching devices and also have a good response in grid-tied PV systems.