A High Frame Rate Analog Front-End IC With Piezoelectric Micromachined Ultrasound Transducers Using Analog Multi-Line Acquisition for Ultrasound Imaging Systems

This paper proposes a high frame rate analog front-end (AFE) IC combined with a piezoelectric micromachined ultrasonic transducer (PMUT) for ultrasound imaging systems (UISs). The proposed AFE IC, which consists of 8-channel transceivers and a peripheral circuit, employs analog multi-line acquisition (AMLA) based on sub-array beamforming. This AMLA generates multiple scanlines during a scan time by simultaneously and precisely controlling the delay of the AFE IC, thus achieving the high frame rate of the AFE IC. The sensitivities of the PMUT for transmitting and receiving ultrasound waves are simulated to be 67.5 kPa/V and 1.2 mV/kPa, respectively, which are high enough to mitigate the needs of the high-voltage electronics for UISs. The proposed AFE IC was fabricated using a 0.18- μm silicon-on-insulator process and occupies an active area of 2.56 mm ×1.68 mm. The measurement results using the simulated PMUT parameters show that the proposed AFE IC with the AMLA precisely controls its delay up to 1 μs at a clock frequency of 40 MHz. It also acquires more than 9,000 scan/s even at a focal depth of 150 mm, which is at least twice greater than those of prior works, achieving a high frame rate of 93 Hz when 100 scanlines are used for a frame. In addition, a figure-of-merit, which considers the energy consumption per channel/scan and the energy loss, is achieved to be 20 nJ/scan/dB at a focal depth of 150 mm and a center frequency of 3.6 MHz; this is the best result compared to previously reported works. Therefore, the proposed AFE IC is suitable for UISs requiring a high frame rate.

SECTION I. Introduction

Ultrasound imaging systems (UISs) have been widely researched for medical applications due to their advantages of non-invasiveness to the human body and real-time imaging capabilities. Especially, to realize high-quality, real-time imaging of heart motions and cardiac events in the UISs, it is necessary to increase the frame rate, which represents a measure of how fast motion can be captured as an image [1]. However, the frame rate of the UISs is physically limited to less than 50 fps at a large focal depth (>10 cm) due to the acoustic velocity and the distance over which the ultrasound wave travels.

Various studies [2]–​[11] have been conducted to overcome the above physical limitation in the frame rate of the UISs. Multi-line acquisition (MLA) using a parallel processing technique based on plane wave imaging [2]–​[6] was reported to increase the frame rate by producing multiple scanlines from transmitted unfocused ultrasound waves at a pulse repetition frequency (PRF). However, these unfocused ultrasound waves caused a poor signal-to-noise ratio (SNR), particularly at a great focal depth. In addition, multi-line transmission (MLT) [7]–​[10] was reported to simultaneously transmit multiple focused beams in different directions, while increasing the frame rate without sacrificing the maximum focal depth or the number of scanlines. However, this MLT caused a large dynamic power in the ultrasound probe during the multiple transmissions of the ultrasound waves and limited the SNR due to crosstalk between the simultaneously transmitted beams [10].

The previous MLAs and MLTs mentioned above have been realized in the digital domain (FPGA or main instrument unit) followed by the analog front-end (AFE) IC and the analog-to-digital converters (ADCs) in the ultrasound probe. Here, the AFE IC transmits high-voltage (HV) signals to the ultrasound transducers and receives echo from the human body. These multi-line implementations in the digital domain have the advantages of generating multiple scanlines and allowing for flexible control of the beam formation. However, this flexible control must constantly adjust the entire delay range for the multiple beam formation even at a fine delay of less than a few micro seconds between the adjacent scanlines, resulting in computational inefficiencies. In addition, as the number of transceiver channels of the AFE IC increases, so does the number of ADCs, which increases the device area and power consumption in implementing the compact ultrasound probe. As such, attempts to increase the frame rate only in the digital domain have led to the aforementioned drawbacks, resulting in incomplete real-time imaging of the UISs. Nevertheless, not much research has yet been dedicated to AFE ICs in the ultrasound probe [12]–​[15] to address the physical limitations in the frame rate of the UISs. In [14], a column-row architecture was employed in the AFE IC to increase the frame rate based on parallel processing with the plane wave; however, this architecture was still limited in terms of increasing the frame rate at a shallow focal depth.

In this paper, an analog multi-line acquisition (AMLA) with a focused beam is proposed to increase the frame rate of the AFE IC based on sub-array beamforming for UISs. The proposed AMLA enables the proposed AFE IC to not only increase the frame rate by controlling only the fine delay, not the full delay, but also mitigate the increase in the number of ADCs. In addition, piezoelectric micromachined ultrasound transducers (PMUTs) have been employed to alleviate the need to use HV electronics in the UISs. As a result, using the HV DC bias is no longer necessary, which is generally tens of volts for capacitive micromachined ultrasonic transducers (CMUTs). Also, these PMUTs achieve better sensitivity due to their higher capacitance and lower electrical impedance than the CMUTs [16].

The remainder of this paper is organized as follows. Section II presents the architecture of the proposed AFE IC employing the AMLA and its operating principle. In Section III, the circuit implementation of the proposed AFE IC is described in detail. Then, the experimental results are analyzed and compared with previous works in Section IV. Finally, the conclusions are given in Section V.

SECTION II. System Architecture

A. Analog Front-End (AFE) IC

Fig. 1 shows the block diagram of the proposed AFE IC that not only transmits HV signals to the PMUT arrays to generate ultrasound waves, but also receives the electronic signals of echo from the human body and performs signal conditioning before the analog-to-digital conversion. The AFE IC consists of two sub-arrays, each of which has 4 transceivers, and a peripheral circuit that includes a control block, a low-voltage differential signaling (LVDS) RX, and differential-to-single-ended (D2S) buffers. Each transceiver performs the TX operation for ultrasound waves through the TX circuit including a TX controller and a biphasic HV pulser, and the RX operation through the RX circuit including a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a multiple analog delay line (MADL). Here, the VGA is employed for time-gain compensation. A protection switch (SW) employing a floating-source structure configured with only three HV devices [17] is implemented to protect the low-voltage devices used in the RX circuit during the TX operation.

FIGURE 1.

Block diagram of the proposed AFE IC with 8 transceivers.

In the peripheral circuit implemented in the AFE IC, the LVDS RX receives an 80 MHz clock signal (CLK$_{\mathrm {80M}}$ ) and serial data ($\text{D}_{\mathrm {AFE\_{}IC}}$ ) from the FPGA, and then sends them to the control block. $\text{D}_{\mathrm {AFE\_{}IC}}$ includes the frequency data, TX fine delay data ($\text{D}_{\mathrm {FD\_{}TX}}$ ), number of pulses for TX operation, and gain control data and RX fine delay data ($\text{D}_{\mathrm {FD\_{}RX}}$ ) for RX operation. Here, each $\text{D}_{\mathrm {FD\_{}RX}}$ is continuously calculated by the FPGA based on the corresponding fine delays. The D2S buffer receives the differential signals (V_OUTP[3:0] and V_OUTN[3:0]) from the MADLs in two sub-arrays and converts them to the single-ended signals (V_OUT[3:0]), followed by sending them to the ADCs. Here, the D2S buffer not only reduces the number of output signals, but also achieves a conversion gain of 6 dB.

For TX operation, the control block delivers $\text{D}_{\mathrm {AFE\_{}IC}}$ with the frequency data, $\text{D}_{\mathrm {FD\_{}TX}}$ , and the number of pulses to the TX circuit that is fully configured with digital circuits. Then, an HV pulse ($\text{V}_{\mathrm {HV\_{}OUT}}$ ) is produced to generate the ultrasound waves in the PMUT. Here, a TX input signal ($\text{V}_{\mathrm {IN\_{}TX}}$ [1:0]) with the coarse delay is provided from the FPGA to trigger the TX controller. Then, the TX controller generates a low-voltage TX signal ($\text{V}_{\mathrm {LV\_{}TX}}$ ) that pulls up and down $\text{V}_{\mathrm {HV\_{}OUT}}$ based on the frequency data and the number of pulses. In addition, $\text{V}_{\mathrm {LV\_{}TX}}$ is delayed based on $\text{D}_{\mathrm {FD\_{}TX}}$ from $\text{V}_{\mathrm {IN\_{}TX}}$ and delivered to the HV pulser, followed by providing the HV pulse to the PMUT.

For RX operation, the RX circuit receives an electrically converted signal (V_IN) from PMUTs and performs an amplification operation through the LNA and VGA, as well as the micro-beamforming operation with the AMLA through the MADL. Here, the control block provides the gain control signals to the VGA and controls fine delays of the MADL based on $\text{D}_{\mathrm {FD\_{}RX}}$ . Then, V_OUT[3:0] from the D2S buffers are converted to digital signals by the ADCs, and then the coarse delays are applied to these digital signals in the FPGA for the beamforming.

B. Analog Multi-Line Acquisition

The proposed AMLA employs sub-array beamforming and produces multiple adjacent scanlines based on echo from the human body as transmitting the single-focused ultrasound beam, thus increasing the frame rate of the UIS. Here, the frame rate can be expressed as

$$\begin{equation*} \textrm {Frame rate}={\mathrm {PRF}}\times \frac {{\mathrm {N_{MLA}}}}{{\mathrm {M}}},\tag{1}\end{equation*}$$ where M is the number of scanlines used for a frame, and N_MLA is the number of scanlines produced by the AMLA at a PRF. The PRF can be calculated by $$\begin{equation*} {\mathrm {PRF}}=\frac {{\mathrm {V_{tissue}}}}{{\mathrm {L}}\times 2}+\frac {1}{{\mathrm {T_{TX}}}},\tag{2}\end{equation*}$$ where V_tissue is the acoustic velocity in soft tissue, which is typically 1540 m/s, L is the focal depth, and T_TX is the time interval for TX.

To properly realize the proposed AMLA, the delay-and-summation (DAS) needs to be applied to the corresponding beam during the beamforming operation of the UISs. Here, the DAS represents that the ultrasound waves generated from the transducer array are delayed based on the delay profile according to the focal points and then summed together to form the beam. It can be implemented with three components: memory for storing the incoming ultrasound waves, a delay controller for applying the delay profile to the ultrasound wave, and circuits for summing the ultrasound waves.

Fig. 2(a), (b), and (c) show the configuration of the proposed AMLA, including the operational block diagram, geometric diagram of the one-dimensional UIS, and delay profiles with the coarse delay (T_CD) and fine delay (T_FD) based on the focal point located at Fig. 2(b), respectively.

FIGURE 2.

Configuration of the proposed analog MLA (AMLA): (a) operational block diagram of the AMLA, (b) geometric diagram of a one-dimensional UIS, and (c) examples of coarse and fine delay profiles.

In Fig. 2(a), the proposed AMLA simultaneously generates multiple RX signals ($\text{W}_{\mathrm {1\_{}0}}$ , $\text{W}_{\mathrm {1\_{}1}}$ , $\text{W}_{\mathrm {2\_{}0}}$ , $\text{W}_{\mathrm {2\_{}1}}$ , and up to $\text{W}_{\mathrm {k\_{}1}}$ ) with different fine delays ($\text{T}_{\mathrm {FD1}}$ (k, n) and $\text{T}_{\mathrm {FD2}}$ (k, n)) applied through the DAS operation during the scan time, where $\text{T}_{\mathrm {FD1}}$ (k, n) and $\text{T}_{\mathrm {FD2}}$ (k, n) represent the fine delays of the $\text{n}^{\mathrm {th}}$ transceiver in the $\text{k}^{\mathrm {th}}$ sub-array in the AFE IC for the 1^st and 2^nd beams, respectively. For example, the 1^st sub-array of the AFE IC at the bottom of Fig. 2(a) stores the ultrasound waves received from the transducer array into the analog memory, combines the stored ultrasound waves with $\text{T}_{\mathrm {FD1}}$ (1, n) and $\text{T}_{\mathrm {FD2}}$ (1, n), and generates $\text{W}_{\mathrm {1\_{}0}}$ and $\text{W}_{\mathrm {1\_{}1}}$ . Here, $\text{W}_{\mathrm {1\_{}0}}$ and $\text{W}_{\mathrm {1\_{}1}}$ correspond to V_OUT[0] and V_OUT[1], as shown in Fig. 1, respectively. Fig. 2(b) shows the geometric diagram of a one-dimensional UIS. At the focal point in the $\text{m}^{\mathrm {th}}$ scanline (FP[m]), the time-of-flight (t_delay) of the ultrasound wave can be expressed as

$$\begin{equation*} \mathrm {t_{delay}} =\frac {\sqrt {\left ({{\mathrm {dx}+\mathrm {R}_{0} \cos \theta } }\right)^{2}+\left ({{{\mathrm {R}}_{0} \sin \theta } }\right)^{2}}}{\mathrm {V_{tissue}}},\tag{3}\end{equation*}$$ where R₀ is the distance between FP[m] and the origin (O) that is the center of the transducer array, $\theta$ is the angle between R₀ and the probe face, dx is the distance between each transducer and O, and V_tissue is the acoustic velocity in soft tissue.

Fig. 2(c) shows the delay profiles of T_FD and T_CD, which are separately applied in the AFE IC and the FPGA, respectively. The total delay ($\text{T}_{\mathrm {d.m}}$ (k, n)) of the $\text{n}^{\mathrm {th}}$ transceiver in the $\text{k}^{\mathrm {th}}$ sub-array with respect to FP[m] can be expressed with T_FD and T_CD as

$$\begin{equation*} \mathrm {T_{d.m} (k,n)}=\mathrm {T_{CD.m} (k)+T_{FD.m} (k,n)},\tag{4}\end{equation*}$$ where $\text{T}_{\mathrm {CD.m}}$ (k) is the coarse delay of the $\text{k}^{\mathrm {th}}$ sub-array and $\text{T}_{\mathrm {FD.m}}$ (k, n) is the fine delay of the $\text{n}^{\mathrm {th}}$ transceiver in the $\text{k}^{\mathrm {th}}$ sub-array for FP[m]. Also, $\text{T}_{\mathrm {CD.m}}$ (k) is the minimum $\text{T}_{\mathrm {d.m}}$ of the transceivers in the $\text{k}^{\mathrm {th}}$ sub-array, which can be expressed as $$\begin{equation*} \mathrm {T_{CD.m} (k)}=\min \nolimits _{\mathrm {n}\in \mathrm {k}} \mathrm {T_{d.m} (k,n)},\tag{5}\end{equation*}$$

In order to increase the frame rate through the proposed AMLA, the MADL in the AFE IC should cover the range of T_FD with respect to FP[m] and its adjacent scanline with the corresponding focal point (FP[m-1]) without changing T_CD. Therefore, the range of T_FD in the MADL should be

$$\begin{align*} 0\!\le \!\mathrm {T_{FD}} \le \max \left[\mathrm {diff}\{{\mathrm {T_{CD.m}}} (1) \},\mathrm {diff}\{\mathrm {T_{CD.m} (k)}\}\right]\!+\!\mathrm {T_{FD\_{}MAX}},\!\!\!\! \\\tag{6}\end{align*}$$ where diff{$\text{T}_{\mathrm {CD.m}}$ (k)} and $\text{T}_{\mathrm {FD\_{}MAX}}$ are the difference in T_CD in the $\text{k}^{\mathrm {th}}$ sub-array between FP[m] and FP[m-1], and the maximum fine delay over all the delay profiles, respectively.

In this way, the AMLA in the proposed AFE IC generates multiple RX signals by controlling only T_FD in Eq. (6), unlike the conventional DMLAs covering the entire delay range; this results in an improvement in the computational efficiency. Moreover, the number of outputs (V_OUT) in Fig. 1 does not increase by a factor of N_MLA, but rather decreases to 4.

C. Piezoelectric Micromachined Ultrasound Transducer

In this work, the PMUT transducer is designed with a focus on optimizing the TX performance to mitigate the needs of the HV electronics. Fig. 3(a) and (b) show the configuration of a PMUT and cross-sectional view of its unit cell, respectively, where one sub-channel of the PMUT is configured with 4 unit cells. The membrane of the unit cell is made of SiO₂ and Si, and its diameter was set to $80~\mu \text{m}$ . In addition, the top electrode (Pt) diameter was determined to be $48~\mu \text{m}$ (60% coverage) considering a maximum TX pressure through the frequency sweeping analysis. Here, Au is used for the top electrode interconnection of the 4 unit cells to configure the PMUT sub-channel. The material of the PZT is PZT-5H, and its thickness is designed to be $1.0~\mu \text{m}$ in order to acquire sufficient acoustic pressure, even when a lower-voltage device is used for the TX circuit. Accordingly, the TX circuit should be carefully designed in consideration of the large capacitance of the PMUT channel of 6.7 nF, which is calculated to be a load capacitance of a unit cell of 34.7 pF $\times 4$ unit cells $\times48$ sub-channels for each transceiver of the AFE IC. The sensitivities of the PMUT used in this work were simulated using COMSOL Multiphysics [18] under the water loading condition. For the TX sensitivity, a single sine wave with 40 V_PP at a center frequency of 3.6 MHz is biased to the PMUT, resulting in a TX acoustic pressure of 2.7 MPa (corresponding to a TX sensitivity of 67.5 kPa/V) at the center surface of the membrane. For the RX sensitivity, it is assumed that a plane wave with an acoustic pressure of 1 kPa propagates 1 mm from human body to the surface of the membrane, resulting in a generation of an RX sensitivity of 1.2 mV_PP. Although the RX sensitivity of this work is ten times less than that of [19] (13.4 mV/kPa), the TX sensitivity of this work, which is about fifteen times greater than that of [19] (3.9 kPa/V), enables 10 V_PP implementation for the TX operation. In addition, the fractional bandwidth (f_BW) is simulated to be 80% at a center frequency of 3.6 MHz under the water loading condition, as shown in Fig. 4. Moreover, the pitch in the array is determined to be $214~\mu \text{m}$ , which is half the wavelength at a center frequency of 3.6 MHz, considering the minimization of the side lobe [20]. Based on the determined pitch, the 1-D linear array with 128 channels has a size of 2.7 cm (lateral) $\times1.0$ cm (elevational). Subsequently, the angular resolution and focused beamwidth are respectively calculated to be 1° and 1.6 mm at focal depth of 10 cm, according to [21].

FIGURE 3.

(a) Top view of a PMUT and (b) cross-sectional view of its unit cell.

FIGURE 4.

Simulated frequency response of the PMUT.

FIGURE 5.

Block diagram of the HV pulser.

SECTION III. Circuit Implementation

A. TX Circuit

The TX circuit in the transceiver shown in Fig. 1 is configured with only digital logics, making it simple and flexible. The TX controller applies $\text{D}_{\mathrm {AFE\_{}IC}}$ to $\text{V}_{\mathrm {IN\_{}TX}}$ so as to generate $\text{V}_{\mathrm {LV\_{}TX}}\text{s}$ for the HV pulser. Here, the frequency, maximum TX fine delay, and number of pulses included in $\text{D}_{\mathrm {AFE\_{}IC}}$ used in this work are 1.2 MHz to 6.67 MHz, $1.6~\mu \text{s}$ , and 0 to 31, respectively.

Fig. 4 shows the HV pulser, which uses two stages (stages 1 and 2) to produce a biphasic waveform. $\text{V}_{\mathrm {LV\_{}TX}}\text{s}$ , including V_PU, V_PD, V_RZU, and V_RZD, are made of 5 V digital signals for pull-up, pull-down, return-to-zero-up, and return-to-zero-down, respectively. Stage 1 pulls the output of the HV pulser ($\text{V}_{\mathrm {HV\_{}OUT}}$ ) up to VDDM (5 V) using V_PU and down to VSSM (−5 V) using V_PD. Then, stage 2 returns $\text{V}_{\mathrm {HV\_{}OUT}}$ to 0 V from 5 V or −5 V and generates biphasic waveforms with V_RZU and V_RZD. Buffers in each stage are implemented to sufficiently drive the load capacitances of laterally diffused MOS (LDMOS) transistors, M1 to M4. Accordingly, the rising and falling times of $\text{V}_{\mathrm {HV\_{}OUT}}$ are determined to be 25 ns to properly generate ultrasound waves in the PMUT array. Level shifters (LSs) are implemented to provide signals with a voltage range of 0 V to −5 V to the buffers so as to drive the pull-down transistors, M2 and M4. The protection diodes, D1 and D2, are implemented only in stage 2 to protect transistors M3 and M4, while preventing $\text{V}_{\mathrm {HV\_{}OUT}}$ from being clamped to 0 V.

B. LNA and VGA in the RX Circuit

Fig. 6 shows the schematics of the LNA and VGA in the RX circuit, which are implemented in each transceiver to amplify the ultrasound waves generated from the PMUT. The gain of the LNA is determined by the maximum amplitude of the ultrasound waves and the ratio of the ADC aperture [22]. Here, the maximum amplitude of the ultrasound waves is determined to be 0.3 V_PP based on the simulated sensitivities of the PMUT, while the conversion range of the ADC is determined to be a supply voltage of 1.8 V. Consequently, the maximum gain of the LNA is determined to be 9.5 dB when considering a D2S buffer gain of 6 dB.

FIGURE 6.

Schematics of (a) LNA and (b) VGA without the common mode feedback circuits.

To reduce the power consumption, the LNA shown in Fig. 6(a) adopts an open-loop-based structure with wide bandwidth [23]. It controls its gain from 3 dB to 9.5 dB by trimming the resistance values in Kelvin switches using a 2-bit register (REG_LNA[1:0]) to avoid signal saturation. Its input (V_IN) is AC-coupled to reduce the noise component and block the DC signal passing through R₁ and C₁, which are designed to have a cut-off frequency of 0.3 MHz. Here, V_IN is converted into the differential signal ($\text{V}_{\mathrm {OUTP\_{}LNA}}$ and $\text{V}_{\mathrm {OUTN\_{}LNA}}$ ) in order to achieve better noise immunity of the AFE IC.

As the ultrasound wave travels through the human body, its energy is exponentially lost. The VGA is employed to compensate for such energy loss of the ultrasound wave, of which the maximum value ($\text{A}_{\mathrm {att.max}}$ ) can be expressed as

$$\begin{equation*} {\mathrm {A}}_{{\mathrm {att}}.\max } =\alpha \times 2\times {\mathrm {d}}_{\max } \times {\mathrm {f}}_{{\mathrm {u}}},\tag{7}\end{equation*}$$ where $\alpha$ is the attenuation coefficient of soft tissue (typically 0.5 dB/MHz/cm), d_max is the maximum focal depth, and f_u is the maximum frequency of the ultrasound wave. Here, $\text{A}_{\mathrm {att.max}}$ is calculated to be 75 dB at a d_max of 15 cm and an f_u of 5 MHz, which is determined by considering an 80% fractional bandwidth at a center frequency of 3.6 MHz. Since the minimum dynamic range required for a display image is considered to be about 42 dB with a margin of 12 dB for image generation [22], the total dynamic range required for the UIS is determined to be 117 dB; this should be achieved through the LNA, VGA, and ADC. Thus, the VGA requires a gain of 29.5 dB when the resolution and SNR of the ADC are assumed to be 12-bit and about 72 dB, respectively. The continuous VGA shown in Fig. 6(b), which consists of an R-2R attenuator, Gaussian interpolator, g_m stage, and main amplifier, is implemented to achieve dB-linear characteristics for exponential energy suppression in the human body. Since each tab in the R-2R attenuator has a gain attenuation of 6 dB, five tabs are selected to cover the gain of 29.5 dB required for the VGA. The g_m stages have the same number of stages as the number of tabs in the R-2R attenuator, and the Gaussian interpolator adjusts the total transconductance value of the g_m stage by using ramp signals, V_CONP and V_CONN. The main amplifier with a fixed gain of 29.5 dB is designed with a current feedback topology to avoid the trade-off between gain and bandwidth.

C. Multiple Analog Delay Line (MADL) in the RX Circuit

Fig. 7(a) shows the block diagram of the MADL in a transceiver of the proposed AFE IC, which employs a pipelined sample-and-hold architecture with a current-splitting method [24] to decrease the power consumption and increase the area efficiency. The MADL is configured with 41 analog memory cells, 4 buffering current sources ($\text{I}_{\mathrm {BUF}}\text{s}$ ), and 4 flipped-voltage-followers (FVFs). The control block receives CLK_80M and $\text{D}_{\mathrm {AFE\_{}IC}}$ from the LVDS RX, and then converts three 6-bit $\text{D}_{\mathrm {FD\_{}RX}}$ in $\text{D}_{\mathrm {AFE\_{}IC}}$ to three 41-bit one-hot-encoded signals (WRITE[40:0], READ₁[40:0], and READ₂[40:0]) to control the analog memory cells of the MADL. An analog memory cell is a unit cell that samples V_INP or V_INN, and applies T_FD to the sampled signal. Considering an extension to 128 channels for the 1-D linear ultrasound probe, the range of T_FD in the MADL is set to $1~\mu \text{s}$ at a sampling frequency of 40 MHz, according to Eq. (6). This results in the implementation of 41 analog memory cells. Fig. 7(b) shows the schematic of the analog memory cell that consists of a buffer; a sampling capacitor (C_MOS) used as an analog memory cell; and three switches, including a writing switch (SW$_{\mathrm {WRITE}}$ ) and two reading switches (SW_READ1 and SW$_{\mathrm {READ2}}$ ). Here, WRITE[i], WRITE_b[i], READ[i], and READ_ b[i] are the write enable signal, write enable bar signal of SW_WRITE, read enable signal, and read enable bar signal of SW_READ, respectively, where bar signals are generated from each analog memory cell (inverters are not shown in Fig. 7(b)). Since the conventional charge-based operation [25] suffers from loss of the data sampled in the sampling capacitor once one reading operation is finished, a voltage-based operation that uses an inserted buffer is employed for the MADL in this work. This makes the sampled data stay in the C_MOS capacitor, thus enabling simultaneous fine-delay control for the proposed AMLA. The FVFs are implemented to shift the DC output voltage level to 1/2 VDD, while driving the fine-delayed differential outputs (V_OUTP[0], V_OUTN[0], V_OUTP[1], and V_OUTN[1]) into D2S buffers. The differential outputs are averaged with the 4-channel transceiver outputs in the sub-array, thus suppressing noise by a factor of two, which is the root of the number of transceivers in the sub-array.

FIGURE 7.

(a) Block diagram of the MADL in the AFE IC and (b) its schematic depicted for a positive signal path only.

For proper read operation, the MADL is implemented in a way to protect the sampled data in C_MOS from distortion, which can be caused by the following factors. First, the clock feedthrough and charge injection of SW_WRITE due to the parasitic capacitances are taken into account by designing both the NMOS and PMOS transistor sizes to be equal. Next, WRITE[i] between the adjacent analog memory cells is designed to avoid overlapping so as to prevent sampled data loss caused by charge sharing. Moreover, the distortion of the sampled data during the transition of the buffer output and the kT/C noise are taken into account by using a large capacitance value of C_MOS of 512 fF, which is 80 times greater than the parasitic capacitance value of M1, considering the 12-bit ADC resolution [24]. In addition, the off-state leakage current flowing through SW_WRITE, which dominantly affects the analog memory cell in the 0.18-$\mu \text{m}$ process used in this work, is investigated through simulation. This shows a negligibly small value of only few pA, which corresponds to less than 1 LSB (0.4 mV) of the voltage variation in C_MOS at a 12-bit ADC resolution during a maximum fine delay of $1~\mu \text{s}$ .

Fig. 8 shows the timing diagram of the MADL with a 4-channel transceiver. The control block generates two clock signals: CLK₁ with 40 MHz and CLK₂ with 1/4 phase-shifted 40 MHz from CLK_80M. This is followed by the production of WRITE[N], which has a width of 18.75 ns (t_WR) that is sufficient for avoiding the distortion due to the charge sharing between the adjacent analog memory cells. When WRITE[N] becomes high, SW$_{\mathrm {WRITE}}\text{s}$ are turned on, followed by sampling V_INP. After that, SW_READ1 and SW_READ2 are turned on when READ₁[N] and READ₂[N] become high, respectively. Then, the proposed AMLA simultaneously generates V_OUTP[0] and V_OUTP[1] according to the fine delay of the sampled data, which is determined by the difference in delays between SW_WRITE[N] and both SW_READ1[N] and SW_READ2[N]. The MADL has a minimum unit delay (t_d), which is determined by a sampling frequency of 40 MHz, and a maximum delay of (N-1) $\times \,\,\text{t}_{\mathrm {d}}$ , as depicted in Fig. 8.

FIGURE 8.

Timing diagram of the MADL with 4-channel transceiver.

SECTION IV. Experimental Results

Fig. 9 shows a microphotograph of the proposed AFE IC, which was fabricated using a 0.18-$\mu \text{m}$ HV SOI process with 1 poly and 6 metal layers, and occupied an active area of 2.56 mm $\times1.68$ mm. Pads for $\text{V}_{\mathrm {HV\_{}OUT}}\text{s}$ and V_OUT[3:0] are located at the top and bottom sides, respectively, where $\text{V}_{\mathrm {HV\_{}OUT}}$ for each channel is double-wire bonded to reduce the voltage drop caused by the resistance and inductance of the wire. In addition, test pads on the left and right sides were implemented to test circuits within the AFE IC. In the measurement of the proposed AFE IC, the TX load of the PMUT was modeled with passive devices on the printed circuit board, and an arbitrary waveform generator was used to supply the RX input signal, where the range is determined based on the simulated sensitivities of the PMUT.

FIGURE 9.

Microphotograph of the proposed AFE IC.

Fig. 10 shows the measurement results of $\text{V}_{\mathrm {HV\_{}OUT}}$ after the TX operation is completed. Here, the operating frequency is selected to be a main frequency of 3.6 MHz, and the number of occurring pulses is set to one. Different fine delays of 375 ns, 175 ns, 75 ns, 25 ns, and a maximum value of $1.6~\mu \text{s}$ are applied to the TX circuits. The measurement results show that each TX circuit produces a 10 $\text{V}_{\mathrm {PP}}~\text{V}_{\mathrm {HV\_{}OUT}}$ with its corresponding fine delay, indicating that the proposed TX circuit works properly.

FIGURE 10.

Measurement results of $\text{V}_{\mathrm {HV\_{}OUT}}$ with different fine delays (375 ns, 175 ns, 75 ns, 25 ns, and $1.6~\mu \text{s}$ from top to bottom).

Fig. 11(a) shows the measured transient waveform of the VGA output ($\text{V}_{\mathrm {OUT\_{}VGA}}$ ) when a 3 mV_PP sine wave with an operating frequency of 3.6 MHz is applied to the input of the AFE IC, given a focal depth of 150 mm. The measurement results show that as V_CONP linearly increases with time, $\text{V}_{\mathrm {OUT\_{}VGA}}$ exponentially increases due to its dB-linear characteristics. This results in an amplification of up to 479 mV, which corresponds to 44.06 dB. In addition, Fig. 11(b) shows the measured transfer function of $\text{V}_{\mathrm {OUT\_{}VGA}}$ , excluding the 6 dB gain of the D2S buffer. This shows the dB-linear characteristics according to V_CONP, while having the gain range from 8.1 dB to 38.3 dB at a center frequency of 3.6 MHz. The measured maximum gain of 38.3 dB is slightly attenuated by 0.7 dB, as compared with a target gain of 39 dB, due to the R-2R attenuator in the VGA and the AC-coupling capacitors, which are used to isolate the DC voltage in the measurement setup. In addition, the cut-off frequency of the high-pass filter was measured to be 0.3 MHz, showing the proper waveform tendency of the band-pass filter. In addition, Fig. 11(c) shows the simulated and measured input referred noises of the LNA and VGA of 1.04 nV/$\surd$ Hz and 1.55 nV/$\surd$ Hz, respectively. The difference between the above simulation and measurement results is the noise caused by the off-chip component on PCB for the PMUT, which is induced into the input of the LNA.

FIGURE 11.

Measurement results of the LNA and VGA according to V_CONP: (a) transient waveform, (b) transfer function, and (c) input referred noise at the maximum gain.

Next, V_OUT[1:0], which are the outputs of the sub-array in the AFE IC, were measured to verify the amplification of the LNA, VGA, and D2S buffers, as well as the MLA operation of the MADL. Fig. 12(a) and (b) respectively show the measured V_OUT[1:0] when different fine delay differences of 25 ns and 975 ns are applied to the $\text{V}_{\mathrm {OUTP\_{}VGA}}$ and $\text{V}_{\mathrm {OUTN\_{}VGA}}$ in the MADL followed by the D2S buffers, producing V_OUT[1:0]. Here, two 6-bit fine delay data, 6’b000001 (25 ns delay) and 6’b000010 (50 ns delay), are simultaneously applied for a 25 ns fine delay difference, whereas a minimum fine delay (25 ns delay, 6’b000001) and a maximum fine delay ($1~\mu \text{s}$ delay, 6’b101000) are simultaneously applied for a 975 ns fine delay difference. In addition, both the measured V_OUT[1:0] were amplified to approximately 420 mV_PP corresponding to 42.9 dB, which is a little less than the target gain of 479 mV_PP corresponding to 44.06 dB. This slight attenuation is caused by the buffers and FVFs of the MADL, each of which has a gain less than unity ($\approx 0.93$ ). Therefore, these measurement results demonstrated that the proposed AFE IC worked properly for the AMLA operation of the MADL and amplification of the LNA, VGA, and D2S buffers.

FIGURE 12.

Measured outputs of a sub array in the AFE IC (V_OUT[1:0]) when the fine delay differences between V_OUT[0] and V_OUT[1] are (a) 25 ns and (b) 975 ns.

Fig. 13 shows the measured FFT (fast Fourier transform) of V_OUT[0] and V_OUT[1] with different fine delays at a center frequency of 3.6 MHz. The amplitudes of the 2^nd and 3^rd harmonic distortions (HD2 and HD3) were measured to be 44.7 dB relative to the carrier (dBc) and 42.8 dBc, both of which are greater than 40 dBc. This shows that the outputs of the proposed AFE IC were little distorted during the amplification and MLA operation.

FIGURE 13.

Measured FFT results of V_OUT[0] and $\text{V}_{ \mathrm {OUT}}[1]$ .

Consequently, the measurement results in Figs. 12 and 13 demonstrate that the proposed AMLA in the proposed AFE IC properly performs simultaneous delay operations, thereby increasing the number of scanlines per second, resulting in an increased frame rate.

Table 1 summarizes the performance comparison of the proposed AFE IC with previous works for UIS applications. The voltage level of the proposed TX circuit was much lower than those of [12], [14], and [15], indicating that the PMUT used in this work can be adequately employed for transducers in low-power UIS applications. The number of scanlines per second (scan/s) can be obtained by a multiplication of the PRF and N_MLA, and the proposed AFE IC achieved the number of scanlines of 23,547 scan/s and 13,344 scan/s at focal depths of 50 mm and 100 mm, respectively, both of which are much greater than those of [12] and [13]. Even with a focal depth of 150 mm, the proposed AFE IC obtained 9,310 scan/s, achieving a frame rate of 93 fps based on Eq. (2) with 100 scanlines for a frame. This shows that the proposed AMLA can achieve a higher frame rate than previous works. Moreover, the proposed AMLA enables the proposed AFE IC to achieve a frame rate of 124 fps with a 3-D image, which is about twice greater than that of [14] with 3-D image, under the same focal depth and viewing angle conditions.

TABLE 1 Performance Summary and Comparison

To properly verify the performance of the proposed AFE IC, a figure-of-merit (FoM) is employed using FoM = (energy consumption per channel/scan)/$\text{A}_{\mathrm {att.max}}$ at the given center frequency and focal depth. This FoM also considers an N_MLA of 2 for the proposed AMLA at a PRF, and the energy loss in dB (A_att). Here, A_att was included in the FoM to consider the energy loss that exponentially increases according to the frequency and focal depth, as expressed in Eq. (7). As a result, the proposed AFE IC achieved an FoM of 20.1 nJ/scan/dB, which is the best value among the compared works, indicating that the proposed AFE IC is very energy efficient, while still achieving the highest frame rate according to the acquired scanlines. Therefore, the proposed AFE IC is suitable for UISs requiring a high frame rate. Moreover, since the proposed work had a much larger target focal depth (150 mm) than [12], [13], its active area of 2.6 mm $\times1.7$ mm became slightly larger; however, this is still a reasonable value for the TX circuit considering the given target focal depth.

Since the proposed AFE IC has a better FoM than previous works and the PMUT used in this work mitigates the need to use HV electronics, it can be easily extended to portable UIS applications requiring less circuit complexity and low energy consumption. Moreover, unlike conventional MLTs that cause large dynamic power consumption problems in portable UISs, the proposed AMLA is not constrained in terms of its power budget for high frame rate applications.

SECTION V. Conclusion

This paper proposes an AFE IC combined with a PMUT array using its simulated parameters to achieve the high frame rates needed for ultrasound imaging systems. The proposed AFE IC employs an AMLA based on a sub-array beamforming architecture to achieve a high frame rate. The MADL in the AFE IC, which operates in the voltage domain, controls different fine delays without losing the stored data during the scan time. In addition, the simulated PMUT used in this work allows for the use of a relatively low voltage at a 3.6 MHz center frequency. The measurement results of the AFE IC using the proposed AMLA demonstrated simultaneous control of fine delays up to $1~\mu \text{s}$ with 25 ns resolution, while also achieving more than 9,000 scan/s at a focal depth of 150 mm; this is at least twice greater than those achieved in prior works. Consequently, this large number of scanlines enabled the proposed AFE IC to achieve a high frame rate of 93 fps when 100 scanlines are used a frame in medical UISs. In addition, the proposed AFE IC achieved the best FoM of 20 nJ/scan/dB at a focal depth of 150 mm. Moreover, the gain and HD2 of the proposed AFE IC were measured to be 42.9 dB and 44.7 dBc, respectively, showing proper RX operations. Therefore, the proposed AFE IC is suitable for UISs requiring a high frame rate.