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A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks | IEEE Conference Publication | IEEE Xplore

A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks


Abstract:

This paper presents hardware-aware training techniques for efficient hardware implementation of feedforward artificial neural networks (ANNs). Firstly, an investigation i...Show More

Abstract:

This paper presents hardware-aware training techniques for efficient hardware implementation of feedforward artificial neural networks (ANNs). Firstly, an investigation is done on the effect of the weight initialization on the hardware implementation of the trained ANN on a chip. We show that our unorthodox initialization technique can result in better area efficiency in comparison to the state-of-art weight initialization techniques. Secondly, we propose training based on large floating-point values. This means the training algorithm at the end finds a weight-set consisting of integer numbers by just ceiling/flooring of the large floating-point values. Thirdly, the large floating-point training algorithm is integrated with a weight and bias value approximation module to approximate a weight-set while optimizing an ANN for accuracy, to find an efficient weight-set for hardware realization. This integrated module at the end of training generates a weight-set that has a minimum hardware cost for that specific initialized weight-set. All the introduced algorithms are included in our toolbox called ZAAL. Then, the trained ANNs are realized on hardware under constant multiplication design using parallel and time-multiplexed architectures using TSMC 40nm technology in Cadence.
Date of Conference: 07-09 July 2021
Date Added to IEEE Xplore: 23 August 2021
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ISSN Information:

Conference Location: Tampa, FL, USA

I. Introduction

Artificial neural networks (ANNs) have been successfully implemented on various design platforms, such as, analog, very large scale integrated circuits (VLSI), etc [1]. ANN is constructed from basic blocks called neuron, shown in Fig. 1 (a). The behavior of each neuron can be defined mathematically as and where n denotes the number of input signals, weights, and ϕ denotes the activation function on the summation. By connecting several cascaded neurons together we can form an ANN, shown in 1 (b), where each circle denotes a neuron.

References

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