A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication

High common-mode rejection ratio (CMRR) of an analog front end (AFE) requires high intrinsic CMRR of the front-end amplifier with high input common-mode (CM) impedance. This article presents a common-mode replication (CM-REP) technique, which replicates the input CM voltage over the front-end amplifier. By eliminating the CM current flow and its mismatch effect, CM-REP improves CMRR and input CM impedance simultaneously. Implementation considerations regarding the input CM range, on-chip, and off-chip parasitics have been discussed with practical techniques incorporated with the proposed CM-REP. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measured instrumentation amplifier (IA) exhibits >130-dB CMRR and 50- $\text{G}\Omega $ input CM impedance at 50/60 Hz concurrently. The >110-dB CMRR is achieved with input CM up to 900 mV_pp and >102-dB total CMRR (TCMRR) is obtained with 1- $\text{M}\Omega \|$ 10-nF mismatch of source impedance. The prototype consumes $1.86~\mu \text{A}$ from a 1.8-V supply and occupies an active area of 0.227 mm².

SECTION I. Introduction

Rejection of common-mode (CM) interference is a fundamental requirement in precision analog design. For sensor interface applications, e.g., wearable bio-potential acquisition [1]–​[6] and bridge readout [7]–​[9], the analog front end (AFE) often sees large CM interference that has to be accommodated by large common-mode rejection ratio (CMRR). For example, for a 0.5-mV electrocardiograph (ECG) signal with 500-mV CM interference to the AFE, a minimum of 120-dB CMRR is required for 60-dB SNR. In practice, however, it is extremely challenging to achieve high CMRR when the imbalance of source impedance is taken into consideration [2]–​[5]. In [2], with the electrode-impedance mismatch increased from 0 to 800 $\text{k}\Omega$ , the CMRR of the overall system was degraded from 102 to 42 dB. Moreover, higher CMRR is required in two-electrode acquisition systems where much larger CM interference has to be considered [10]–​[12]. The total CMRR (TCMRR) is determined by the intrinsic CMRR of the front-end instrumentation amplifier (IA) as well as the mismatch of source impedance, while the latter has to be accommodated by large input CM impedance.

Chopper-stabilization technique enhances CMRR by modulating the low-frequency errors to a chopping frequency [13]. However, it is found that chopping induces considerable input current noise due to charge injection and clock feed-through, which may dominate the overall noise contribution for high-impedance front ends [14]. Meanwhile, the input differential-mode (DM) impedance is degraded significantly by the chopping process [15], resulting in signal attenuation in high-impedance readout. Similarly, auto-zero technique mitigates the low-frequency errors at the cost of noise folding and switching induced current noise [13]. Moreover, the matching of passive components can be improved with trimming or tuning on-chip [16] or externally [3].

To mitigate the effect of source impedance mismatch, high input impedance is required for the front-end IA. The buffer-based AFE exhibits high input impedance at the cost of power and area consumed by the active buffers [17], [18]. Positive feedback technique boosts the input DM impedance effectively to prevent signal attenuation [15], [19]. However, the input CM impedance is degraded, resulting in the degradation of the TCMRR. Pre-charging technique improves both CM and DM impedance [20], [21]. However, this structure involves chopping, which induces current noise.

The traditional three-opamp implementation of IA is able to provide good CMRR with high input impedance [22]. However, it is usually power-hungry with three opamps driving resistive loads. By sharing the output stage, current-feedback IA consumes less power and the CMRR is no longer limited by the mismatch of passive components [7], [23]. The matching of the input transconductor determines the CMRR, and the mismatch between the two transconductors affects gain accuracy. The power efficiency of current balancing IA is further improved with only one transconductor [24]–​[26]. It is also shown that supply regulation is able to enhance the TCMRR [5], [6], [27], while the extra power regulator is less efficient for systems with a fewer number of channels.

This work proposes a concise approach to high-CMRR design with concurrent high input CM impedance. By replicating the input CM voltage along with the DM signal, the CM current flow is eliminated, which improves both CMRR and input CM impedance. The detailed analysis on the mechanism and design considerations of the common-mode replication (CM-REP) technique are studied. The proposed design accommodates a wide range of input CM with robustness to parasitics on-chip and off-chip. Due to the reuse of the traditional common-mode feedback (CMFB) loop, the implementation is compact. The demonstrated two-stage IA achieves >130-dB CMRR with 50-$\text{G}{\Omega }$ input CM impedance simultaneously, consuming only $1.86~\mu \text{A}$ from 1.8 V.

This work was first introduced in [28]. The complete study with additional details and considerations is presented here. Section II describes the principle of the proposed CM-REP technique with a discussion on the design considerations. Section III presents the circuit design of the core OTA, and Section IV discusses the overall implementation of the IA. Section V shows the measurement results. Also, this article is concluded in Section VI.

SECTION II. CM-REP: Principle and Considerations

A. Principe of CM-REP

Fig. 1 shows an interface model for the analysis of the TCMRR, where $Z_{\text {S}}$ is the source impedance with $Z_{\text {S1}}$ and $Z_{\text {S2}}$ representing the potentially imbalanced differential paths and $Z_{\text {CM}}$ is the input CM impedance of the IA with $Z_{\text {CM1}}$ and $Z_{\text {CM2}}$ for the differential paths. Assuming that the IA has much higher input impedance compared to $Z_{\text {S}}$ , the TCMRR can be expressed as $$\begin{equation*} \frac {1}{\text {TCMRR}}=\frac {{Z_{\text {S}}}}{{Z_{\text {CM}}}}\sqrt {\sigma _{Z_{\text {S}}}^{2}+\sigma _{Z_{\text {CM}}}^{2}}+\frac {1}{\text {CMRR}_{\text {IA}}}\tag{1}\end{equation*}$$ where $\sigma _{Z_{\text {S}}}$ and $\sigma _{Z_{\text {CM}}}$ are the relative mismatch of $Z_{\text {S}}$ and $Z_{\text {CM}}$ , respectively, and CMRR_IA is the intrinsic CMRR of the front-end IA. $Z_{\text {S}}$ and $\sigma _{Z_{\text {S}}}$ are determined by the specific application, e.g., 1-$\text{M}\Omega \|$ 10-nF impedance was suggested to model the dry-contact electrodes [1]. Therefore, a large $Z_{\text {CM}}$ is required to accommodate the mismatch of source impedance. To achieve a high TCMRR, the front-end IA has to exhibit high CMRR and high input CM impedance concurrently. It is worth mentioning that the mismatch of the input CM impedance, $\sigma _{Z_{\text {CM}}}$ , contributes also to the TCMRR degradation. As an on-chip imperfection, it is normally much smaller than $\sigma _{Z_{\text {S}}}$ and can be handled in the same way by a large $Z_{\text {CM}}$ .

Fig. 1.

Interface model for the analysis of the TCMRR.

Fig. 2 shows the idea behind the proposed CM-REP technique, where a fully differential amplifier is depicted with an ideal OTA in a feedback configuration. In the traditional design, as shown in Fig. 2(a), the output CM is stabilized at a fixed voltage by the internal CMFB. Conceptually, the output is a CM virtual ground with an ideal CMFB. The CM current flows from the input to the output through $Z_{\text {A}}$ and $Z_{\text {B}}$ $$\begin{equation*} I_{\text {CM}}= \frac {V_{\text {I},\text {CM}}}{Z_{\text {A}}+Z_{\text {B}}}.\tag{2}\end{equation*}$$

Fig. 2.

Illustration of the CM voltage and current in (a) traditional amplifier and (b) proposed amplifier with CM-REP technique.

This CM current determines the input CM impedance $$\begin{equation*} Z_{\text {CM}}=Z_{\text {A}}+Z_{\text {B}}.\tag{3}\end{equation*}$$

The mismatch in $Z_{\text {A}}$ and/or $Z_{\text {B}}$ results in the mismatch of the CM current, which determines the CMRR of the amplifier $$\begin{equation*} \text {CMRR}=\frac {{Z_{\text {B}}}}{{Z_{\text {A}}}} \cdot \frac {{Z_{\text {A}}}({Z_{\text {A}}+Z_{\text {B}}})}{\left |{ Z_{\text {A1}}Z_{\text {B2}}-Z_{\text {A2}}Z_{\text {B1}}}\right | }.\tag{4}\end{equation*}$$

From the current point of view, if $I_{\text {CM}}$ can be eliminated, $Z_{\text {CM}}$ will be enhanced to infinite. Moreover, the mismatch of $I_{\text {CM}}$ will be eliminated as well, resulting in an infinite CMRR. As illustrated in Fig. 2(b), by replicating the input CM voltage to the output, the CM current, $I_{\text {CM}}$ , is eliminated, improving $Z_{\text {CM}}$ and CMRR simultaneously.

This intuition can be proofed theoretically by incorporating the CM gain, $A_{\text {CM}}=V_{\text {O,CM}}/V_{\text {I,CM}}$ , into a general derivation $$\begin{align*} {Z_{\text {CM}}}'=&\frac {Z_{\text {A}}+Z_{\text {B}}}{1-A_{\text {CM}}}=\frac {Z_{\text {CM}}}{1-A_{\text {CM}}}\tag{5}\\ \text {CMRR}'=&\frac {{Z_{\text {B}}}}{{Z_{\text {A}}}} \cdot \frac {{Z_{\text {A}}}({Z_{\text {A}}+Z_{\text {B}}})}{\left |{ Z_{\text {A1}}Z_{\text {B2}}-Z_{\text {A2}}Z_{\text {B1}}}\right | } \cdot \frac {1}{1-A_{\text {CM}}} \\=&\frac {\mathrm {CMRR}}{1-A_{\text {CM}}}.\tag{6}\end{align*}$$

In the traditional amplifier, $A_{\text {CM}}=0$ , and thus, (5) becomes (3) and (6) becomes (4), while for the amplifier with replicated CM voltage, $A_{\text {CM}}=1$ , resulting in infinite $Z_{\text {CM}}$ and CMRR.

Comparing with existing techniques that are mostly trying to improve the matching, e.g., by sophisticated trimming or tuning [16], [22], the proposed CM-REP technique provides a conceptually different approach, which allows a concurrent improvement on CMRR as well as input CM impedance.

B. Circuit Implementation and Considerations

Fig. 3 shows an implementation of the CM-REP in an amplifier with capacitive feedback, where the input CM is extracted by the two capacitors ($C_{\text {CME}}$ ) and buffered to an input of the CM error amplifier (CMEA). The other input of the CMEA is the extracted output CM of the amplifier. Therefore, the feedback loop sets the output CM in a way similar to the traditional CMFB loop with a dc reference, comparing to which, only an extra CM extraction circuit is exploited. As a result, a global CM is established, eliminating any CM current.

Fig. 3.

Implementation of CM-REP in an amplifier with capacitive feedback.

The accuracy of the CM-REP is primarily determined by the CM extraction, where the parasitic capacitance, $C_{\text {P,CME}}$ , attenuates the CM by a factor of $2C_{\text {CME}}/(2C_{\text {CME}}+C_{\text {P,CME}})$ . As a result, 1% parasitics will limit the CMRR improvement to 40 dB. Similar consideration applies at the other input of the CMEA.

The parasitic capacitance at the input node of the OTA, $C_{\text {P,CM}}$ , provides a ground path for the CM current, degrading both CMRR and $Z_{\text {CM}}$ . Ignoring the mismatch of $C_{\text {A}}$ and $C_{\text {B}}$ and assuming $C_{\text {A}}\gg C_{\text {P,CM}}$ and $C_{\text {A}}\gg C_{\text {B}}$ $$\begin{align*} \text {CMRR}\approx&\frac {C_{\text {A}}}{\Delta C_{\text {P,CM}}} \tag{7}\\ Z_{\text {CM}}\approx&\frac {1}{sC_{\text {P,CM}}}.\tag{8}\end{align*}$$

In general, the performance of CM-REP is limited by the parasitics at these sensitive nodes. Ideally, any CM current path through the parasitics should be prohibited. This can be achieved by shielding the parasitics with the global CM. As shown in Fig. 3, CM shielding is exploited for $C_{\text {CME}}$ , $C_{\text {A}}$ , $C_{\text {B}}$ , and the routing lines at the input of the OTA. Fig. 4 shows a 3-D view of the implementation for an MIM cap array with a routing line. The cap array is placed inside a cavity constructed by metal layers, shielding both vertically and horizontally. The routing line is shielded by the adjacent metals. A unity-gain buffer is exploited to ensure sufficient driving of all shielding cavities.

Fig. 4.

3-D view of the shielding implementation for an MIM cap with routing.

Consequently, the CM performance of the amplifier will be determined by the design of the OTA, where the parasitics at internal nodes and active devices cannot be accommodated by straightforward shielding.

SECTION III. OTA Design

Fig. 5 shows the detailed schematic of the main OTA with CMEA. For higher power efficiency, the N-P complementary input is used, and the input transistors are biased in the subthreshold region [29]. As discussed in Section II, it is important to prevent any CM current flow at the sensitive nodes or, equivalently, to bias those nodes at the global CM replicated from the input. Therefore, in this design, the impedance-boosted tail current sources are exploited, and all cascode transistors are bootstrapped by the self-regulating bias (SRB).

Fig. 5.

Schematic of the main OTA with CMEA.

A. Self-Shielding With SRB

Fig. 6 shows the CM equivalent circuit of a cascode stage with SRB. Intuitively, the source CM of M₁, $V_{\text {S,CM}}$ , follows the input CM, $V_{\text {G,CM}}$ ; and $V_{\text {D,CM}}$ follows the gate CM of the cascode transistor M₃, which in turn follows $V_{\text {S,CM}}$ by the self-regulating process. As a result, both $V_{\text {D,CM}}$ and $V_{\text {S,CM}}$ are bootstrapped to $V_{\text {G,CM}}$ , shielding the parasitics $C_{\text {GS}}$ and $C_{\text {GD}}$ .

Fig. 6.

CM equivalent circuit of a cascode stage with SRB.

The CM gain can be derived mathematically from Fig. 6, giving $$\begin{align*} \frac {V_{\text {S},\text {CM}}}{V_{\text {G},\text {CM}}}=&\frac {({A_{\text {CM}}}'+A_{{1}}+A_{{1}}A_{{3}})R_{\text {T}}} {r_{\text {o1}}+r_{\text {o3}}+A_{{3}}r_{\text {o1}}+R_{\text {T}}+A_{{1}}R_{\text {t}}+A_{{1}}A_{{3}}R_{\text {T}}} \tag{9}\\ \frac {V_{\text {D},\text {CM}}}{V_{\text {G},\text {CM}}}=&\frac {{A_{\text {CM}}}'r_{\text {o1}}-A_{1}r_{\text {o3}}+({A_{\text {CM}}}'+{A_{\text {CM}}}'A_{{1}}+A_{{1}}A_{{3}})R_{\text {T}}} {r_{\text {o1}}+r_{\text {o3}}+A_{{3}}r_{\text {o1}}+R_{\text {T}}+A_{{1}}R_{\text {T}}+A_{{1}}A_{{3}}R_{\text {T}}} \\ {}\tag{10}\end{align*}$$ where $A_{{1}}$ and $A_{{3}}$ are the intrinsic gain of M₁ and M₃, respectively. $A_{{1}}=g_{\text {m1}}r_{\text {o1}}$ and $A_{{3}}=g_{\text {m3}}r_{\text {o3}}$ , where $r_{\text {o1}}$ and $r_{\text {o3}}$ are the drain–source impedance of M₁ and M₃, respectively. $R_{\text {T}}$ is the boosted impedance of the tail current source, $R_{\text {T}}=(1+A_{\text {B}}A_{\text {T2}})r_{\text {o,T1}}+r_{\text {o,T2}}$ . Without loss of generality, ${A_{\text {CM}}}'$ is the CM gain determined by the common-mode loop, which is 0 with traditional CMFB and tends to be 1 with CM-REP. Due to the large $R_{\text {T}}$ , the last term dominates over both the numerators and the denominators in (9) and (10), resulting in a CM gain of 1 in both cases. Assuming 40-dB intrinsic gain of a single transistor with equal $r_{\text {o}}$ , the error is less than $10^{\text {-4}}$ . Therefore, with SRB, all internal CM voltages of the cascode stage are bootstrapped to the input CM.

It is worth mentioning that the self-shielding effect of the SRB does not rely on the CM-REP, as suggested by (9) and (10), where the contribution of ${A_{\text {CM}}}'$ is negligible. To cope with the imperfections associated with the body, e.g., body effect, parasitics, the input and cascode transistors are placed in the same well, as shown in Fig. 5. The SRB has also been exploited in the CMEA and the CM buffer.

B. Input CM Range of OTA

With SRB and CM-REP, a comparative study suggests an additional benefit on the enhanced input CM range. For the standard constant-voltage bias, as shown in Fig. 7(a), the gate–drain and source voltages of the cascode transistor are all fixed, and therefore, the input transistor might be pushed into the linear region with a large input CM voltage. For the SRB shown in Fig. 7(b), the gate and source voltages of the cascode transistor are following the input CM. Compared with the fixed bias, SRB guarantees the input transistor’s operation, allowing a more stable input transconductance and input-referred noise (IRN) performance under input CM variations. However, since the drain voltage of the cascode transistor is still fixed by the CMFB, the cascode transistor can still be pushed into the linear region with a large input CM. Incorporating CM-REP into the SRB, as shown in Fig. 7(c), the voltages at all terminals are able to follow the input CM, guaranteeing the stable operation of both input and cascode transistors as long as the voltage headroom for the tail current source is sufficient.

Fig. 7.

CM voltage illustration of a cascode stage with (a) constant-voltage bias, (b) SRB, and (c) SRB together with CM-REP.

Fig. 8 simulates the input CM range with the three biasing schemes described in Fig. 7. It is shown that with a traditional constant bias, the input CM range is only 0.2 V, which can be improved to 0.45 V with SRB. Significant enhancement is observed when SRB and CM-REP are exploited together, where 1.1-V input CM range is achieved. The simulation result matches very well with the above analysis.

Fig. 8.

Input CM range simulation of the main OTA with the biasing schemes described in Fig. 7 for (a) input transconductance, (b) IRN, and (c) dc gain.

SECTION IV. Two-Stage IA

A two-stage IA is implemented to demonstrate the proposed techniques, as shown in Fig. 9. The first stage employs CM-REP, offering high CMRR with high input CM impedance concurrently. The replicated CM at the output of the first stage is canceled by the chopper-stabilized second stage, which also serves for programmable gain control. For practical considerations, neutralization of ESD parasitics and shielding of PCB parasitics are implemented. The input DM impedance is also enhanced with the positive feedback.

Fig. 9.

Schematic of the proposed two-stage IA with CM-REP.

A. Accuracy of CM-REP

From Fig. 9, the CM gain $A_{\text {CM}}$ from the input to the output of the first stage can be written as $$\begin{equation*} A_{\text {CM}}= \frac {\frac {s}{\omega _{\text {p1}}}}{1+\frac {s}{\omega _{\text {p1}}}} \cdot \frac {1}{1+\frac {1}{A_{\text {CMB}}}+\frac {s}{\omega _{\text {p2}}}} \cdot \frac {1}{1+\frac {1}{A_{\text {CMFB}}}+\frac {s}{\omega _{\text {p3}}}}\tag{11}\end{equation*}$$ where $\omega _{\text {p1}}=1/(R_{\text {CME}}C_{\text {CME}})$ and $\omega _{\text {p2}}$ and $\omega _{\text {p3}}$ are the unity-gain bandwidth of the CM buffer and the CMFB loop, respectively. $A_{\text {CMB}}$ and $A_{\text {CMFB}}$ are the open-loop gain of the CM buffer and CMFB loop, respectively.

The dc zero due to $\omega _{\text {p1}}$ results in a low-frequency error in $A_{\text {CM}}$ , which degrades the accuracy of CM-REP. To mitigate this effect, a very large bias resistor, $R_{\text {CME}}$ , is required. Fig. 10 shows the circuit implementation of $R_{\text {CME}}$ using the switch-off resistance of the PMOS transistors. According to simulation, 2-$\text{T}\Omega$ resistance can be obtained. With this large resistance, however, even a sub-pA leakage current results in a voltage drop of hundreds of mV. In this design, a leakage-biased buffer is adopted to compensate for the leakage current through the substrate diode. The buffer consumes only 7 nA at room temperature. It has also been shown that the leakage bias is able to adjust adaptively with temperature [30].

Fig. 10.

Implementation of large resistance with substrate leakage compensation.

It is worth mentioning that the CM-REP can be turned off when $V_{\text {SET}}$ is set to high, as shown in Fig. 10, then the CMEA sees a fixed voltage $V_{\text {REF}}$ , and in turn, the CMFB loop becomes conventional. This setup allows a measurement comparison.

A large gain of $A_{\text {CMB}}$ and $A_{\text {CMFB}}$ is also required for accurate replication. From (11) and (6), a 40-dB CMRR improvement is expected with 46-dB gain of $A_{\text {CMB}}$ and $A_{\text {CMFB}}$ , which can be easily obtained in 0.18-$\mu \text{m}$ CMOS technology. In this work, the CMFB loop shown in Fig. 5 exhibits 104-dB $A_{\text {CMFB}}$ with a unity-gain bandwidth of 220 kHz. Fig. 11 shows the schematic of the CM buffer, which exhibits 95-dB $A_{\text {CMB}}$ and 65-kHz unity-gain bandwidth with 5-pF load. Moreover, the input parasitics at the CM buffer, CMEA, and the CMFB loop also affect the accuracy of CM-REP. According to (6), 40-dB CMRR improvement requires ≤1% parasitics in the CM path, which is ensured by the shielding and SRB techniques with small-sized input transistors.

Fig. 11.

Schematic of the CM buffer.

B. Pseudo-Resistors

Very large pseudo-resistors are typically employed in capacitive feedback IAs to bias the input of the OTA and provide a sufficiently small high-pass corner [31]. With globally replicated CM, however, as shown in Fig. 12(a), there is a CM current path through the substrate diode of the pseudo-resistor, degrading CMRR. In this design, the substrate is driven by the replicated CM, $V_{\text {CME}}$ , as shown in Fig. 12(b), preventing the diode leakage from affecting the CM-REP while keeping the source-body parasitics shielded.

Fig. 12.

Substrate diode-induced CM current leakage of (a) conventional pseudo-resistor and (b) proposed pseudo-resistor with CM driven substrate.

The noise of the pseudo-resistor can be analyzed from Fig. 13. The IRN contributed by $R_{\text {B}}$ can be written as $$\begin{equation*} \overline {V_{n,R_{\text {B}}}^{2}} =\frac {8kT}{R_{\text {B}}}\frac {1}{\left ({2\pi fC_{\text {A}} }\right) ^{2}} =\frac {8kTR_{\text {B}}}{f^{2}}\left ({\frac {f_{\text {HPF}}}{A_{\text {DM}}} }\right) ^{2}\tag{12}\end{equation*}$$ where $f_{\text {HPF}}$ denotes the high-pass corner frequency and equals $1/(2\pi R_{\text {B}}C_{\text {B}})$ and $A_{\text {DM}}$ is the mid-band gain and equals $C_{\text {A}}/C_{\text {B}}$ . Therefore, the noise is of $1/f^{2}$ characteristic. The root-mean-square (RMS) noise voltage can be derived as $$\begin{equation*} \overline {V_{n,\text {rms},R_{\text {B}}}}=\sqrt {\int _{f_{\text {HPF}}}^{f_{\text {BW}}}{\frac {8kTR_{\text {B}}}{f^{2}}\left ({\frac {f_{\text {HPF}}}{A_{\text {DM}}} }\right) ^{2}df}} \!\approx \!\frac {1}{A_{\text {DM}}}\sqrt {\frac {4kT}{\pi C_{\text {B}}}}\tag{13}\end{equation*}$$ where $f_{\text {BW}}$ is the noise bandwidth under consideration and is often much larger than $f_{\text {HPF}}$ . It is shown that with a fixed $A_{\text {DM}}$ , the noise contribution of the pseudo-resistor is determined by the feedback capacitor $C_{\text {B}}$ , which is further limited by the gain and area considerations.

Fig. 13.

Single-ended circuit model for noise analysis.

With $A_{\text {DM}}$ of 100 and $C_{\text {B}}$ of 200 fF, as used in this design, the calculated RMS noise from (13) is about $1.6~\mu \text{V}_{\text {rms}}$ , dominating the low-frequency noise contribution.

C. ESD and PCB Parasitics

As the front end, the parasitic capacitance around the input path degrades the input CM impedance and consequently, as discussed with (1), the TCMRR. The parasitics are mainly contributed by the on-chip ESD and the off-chip input traces on PCB.

In this work, CM neutralization is exploited to deal with the ESD parasitics. Fig. 14 shows the detailed CM current neutralization implemented in Fig. 9. By connecting the bottom plate of ${C_{\text {CMN}}}$ to the amplified $V_{\text {CME}}$ , an equivalent negative capacitance, ${C_{\text {EQ}}}$ , is generated $$\begin{equation*} C_{\text {EQ}}= -\frac {C_{\text {X}}}{C_{\text {Y}}}C_{\text {CMN}}.\tag{14}\end{equation*}$$

Fig. 14.

CM current neutralization for ESD parasitics.

This negative capacitance compensates for the ESD parasitics from the capacitance point of view [3] or provides the $C_{\text {ESD}}$ -induced current from the current point of view. As a result, the input loading from ESD parasitics is mitigated.

In this design, the estimated $C_{\text {ESD}}$ is 400 fF, and $C_{\text {EQ}}$ is set as −350 fF to avoid over compensation. Operating in CM, the neutralization loop does not result in noise degradation. Therefore, the current requirement is relaxed. With a basic five-transistor OTA, the CM neutralization consumes 160 nA in total.

Moreover, a dedicated CM buffer is employed to shield the PCB parasitics, as shown in Fig. 9, consuming 200 nA.

D. Second-Stage Amplifier

As discussed earlier, a programmable-gain amplifier (PGA) is employed as the second stage, which cancels the replicated CM from the first stage. The CMRR of the IA can be written as $$\begin{equation*} \frac {1}{\text {CMRR}_{\text {IA}}}=\frac {1}{\text {CMRR}_{\text {Amp1}}}+\frac {A_{\text {CM}}}{A_{\text {DM}}} \cdot \frac {1}{\text {CMRR}_{\text {Amp2}}}.\tag{15}\end{equation*}$$

The CMRR of the second stage, $\text {CMRR}_{\text {Amp2}}$ , is scaled down by a factor of $A_{\text {DM}}/A_{\text {CM}}$ . In this design, for a target of 140-dB $\text {CMRR}_{\text {IA}}$ with 40-dB $A_{\text {DM}}$ , $\text {CMRR}_{\text {Amp2}}$ is designed to be larger than 100 dB. A chopper-stabilized capacitively coupled IA is adopted here, as shown in Fig. 15, where the chopping frequency is 10 kHz. A dc blocking capacitor, $C_{\text {R}}$ , is placed before the output chopper to mitigate the output ripple [20]. Meanwhile, a positive feedback capacitor, $C_{\text {PF}}$ , is adopted to improve the input DM impedance. The gain control is implemented by configuring the input capacitance, providing 6–24-dB programmable gain with a 6-dB step.

Fig. 15.

Schematic of the second-stage amplifier with programmable gain control.

E. Noise Analysis

From Fig. 13, the IRN of the overall IA can be calculated as $$\begin{align*}\hspace {-0.5pc}\overline {V_{n,\text {total}}^{2}}=&\left ({\frac {C_{\text {A}}+C_{\text {B}}+C_{\text {P}}}{C_{\text {A}}} }\right) ^{2}\overline {V_{n,\text {OTA}}^{2}} \\&\qquad \qquad +\,\frac {8kT}{R_{\text {B}}}\frac {1}{\left ({2\pi fC_{\text {A}} }\right) ^{2}}+ \left ({\frac {C_{\text {B}}}{C_{\text {A}}} }\right) ^{2}\overline {V_{n,\text {Amp2}}^{2}} \tag{16}\end{align*}$$ where $\overline {V_{n,\text {OTA}}^{2}}$ and $\overline {V_{n,\text {Amp2}}^{2}}$ are the IRN of the first-stage OTA and the second-stage amplifier, respectively, and $C_{\text {P}}$ is the DM parasitics at the virtual ground of the OTA. With 40-dB gain at the first stage, the noise contributed by the second stage is negligible. The second term represents the noise contribution of the feedback pseudo-resistors, which is of $1/f^{2}$ characteristic and exists mainly at lower frequencies, as discussed in Section IV-B.

The OTA contributes flicker noise as well as white noise. In this work, the flicker noise is designed smaller than the $1/f^{2}$ noise of the pseudo-resistors. The white noise is optimized with the current reuse and deep sub-threshold biasing of the input transistors.

SECTION V. Measurement Results

The two-stage IA with the proposed CM-REP technique has been fabricated in a 0.18-$\mu \text{m}$ standard CMOS technology, occupying an active area of $630\times 360\,\,\mu \text{m}^{2}$ , as shown in Fig. 16. The IA draws $1.86~\mu \text{A}$ from a single 1.8-V supply. Table I gives the detailed breakdown of the current consumption, where the CM extraction consumes only 200 nA. This can be considered a dedicated cost for the proposed CM-REP loop since all other blocks are basically reused from the traditional CMFB loop.

TABLE I Current-Consumption Breakdown

Fig. 16.

Die microphotograph of the fabricated amplifier.

Fig. 17 shows the measured gain of the IA prototype, where the gain is configurable from 46 to 64 dB with a 6-dB step, and the bandwidth is from 0.5 to 5 kHz.

Fig. 17.

Measured gain with PGA control.

Fig. 18 shows the measured CMRR of ten samples, where the CMRR of the amplifier is given in Fig. 18(a). Without CM-REP, the CMRR is 85–90 dB at 50/60 Hz. The proposed CM-REP is able to enhance the CMRR to the level above 130 dB at 50/60 Hz, where >40-dB improvement is achieved. At lower frequencies, the CMRR enhancement is limited by the high-pass behavior of the CM extraction, as discussed in Section IV-A, whereas at higher frequencies, the finite bandwidth of the CM buffer and CMEA degrades the effect of CM-REP. 200-mV_PP input CM amplitude is used in the measurement, unless otherwise stated.

Fig. 18.

Measured CMRR of ten samples. (a) CMRR w/ and w/o CM-REP. (b) TCMRR with 1-$\text{M}\Omega \|$ 10-nF mismatch of source impedance.

Fig. 18(b) shows the TCMRR with 1-$\text{M}\Omega \|$ 10-nF mismatch of source impedance, as adopted from the impedance model of dry-contact electrodes in bio-signal acquisitions [1]. With 100% mismatch of input impedance, >102-dB TCMRR is able to be achieved across the measured ten samples. As discussed in Section II-A, this is guaranteed by the high input CM impedance.

Fig. 19 shows the measured input impedance, where 50-$\text{G}\Omega$ input CM impedance at 50 Hz is achieved due to the proposed CM-REP technique with ESD CM neutralization. The measured input DM impedance is 1.6 $\text{G}\Omega$ at 50 Hz. Fig. 20 shows the measured input CM impedance at 50 Hz over ten samples.

Fig. 19.

Measured input CM and DM impedance.

Fig. 20.

Measured input CM impedance at 50 Hz over ten samples.

Fig. 21 shows the measured CMRR at 50 Hz over different input CM amplitudes. Due to the SRB exploited together with CM-REP, as discussed in Section III-B, >110-dB CMRR has been achieved with input CM up to 900 mV_PP. The 20-dB degradation is mainly due to the limited CM range of the telescopic CM buffer.

Fig. 21.

Measured CMRR versus input CM amplitude at 50 Hz.

The measurement has also been carried out under variations over 1.5–2.1-V supply and 0–50 °C temperature, and the measured CMRR at 50 Hz is given in Fig. 22.

Fig. 22.

Measured 50-Hz CMRR with supply and temperature variations.

Fig. 23 shows the measured IRN. The integrated noise is $1.73~\mu \text{V}_{\text {rms}}$ over 0.5–200 Hz and $2.70~\mu \text{V}_{\text {rms}}$ over 200–5 kHz. The total IRN over 0.5–5 kHz is $3.14~\mu \text{V}_{\text {rms}}$ . The thermal noise floor is 39 nV$\sqrt {\text {Hz}}$ . The low-frequency noise is of $1/f^{2}$ characteristic, implying the dominant contribution from the feedback pseudo-resistors, as discussed in Section IV-B.

Fig. 23.

Measured IRN.

Fig. 24 shows the measured total harmonic distortion (THD) versus input DM amplitude over 0.8–3.2 mV_PP. Fig. 25 shows the measured PSRR, which is >102 dB over 0.5–5-kHz bandwidth.

Fig. 24.

Measured THD versus input DM amplitude.

Fig. 25.

Measured PSRR.

Finally, Table II summarizes the measured performance with comparison with the state-of-the-art IAs. It is shown that the IA with the proposed CM-REP excels in terms of the CMRR of the IA, the TCMRR with strong imbalance of source impedance, and input CM impedance simultaneously.

TABLE II Performance Summary and Comparison With Previous Work

SECTION VI. Conclusion

In this article, the CM-REP technique was proposed and demonstrated by the fabricated IA achieving high CMRR and high input CM impedance concurrently. It was shown from the analysis that, high TCMRR of an AFE requires high CMRR of the front-end amplifier as well as high input CM impedance, which accommodates the potential imbalance of source impedance. The proposed CM-REP replicates the input CM along with the DM signal, preventing CM current flow and, consequently, the mismatch of CM current, which improves both CMRR and input CM impedance. The circuit implementation of CM-REP is concise due to the reuse of the traditional CMFB loop, where only a CM extraction is additionally exploited. Practical considerations on the imperfections, including parasitics at sensitive nodes, input CM range, ESD, and PCB parasitics, have been discussed. The fabricated IA prototypes demonstrate >130-dB CMRR and >102-dB TCMRR with 1-$\text{M}\Omega \|$ 10-nF mismatch of source impedance and 50-$\text{G}\Omega$ input CM impedance at 50/60 Hz simultaneously. The performance excels state-of-the-art IAs.