Analysis of Double-Gate Junctionless MOSFET for Energy Efficient Digital Application

In this work, the performance of a Double-Gate Junctionless MOSFET (DGJLT) is reported for low power digital applications. The model is based physically, considering both the inversion and accumulation operating conditions. The analysis demonstrates the transistor behavior in the sub-threshold regime. SILVACO ATLAS TCAD tool is used extensively to validate the results of the proposed circuits. DGJLT transistors are found to have overall better performance at low supply voltage significantly. Hence, DGJLT transistor-based Inverter has been adopted for the reference. Analytical models of power dissipation, delay and power delay product (PDP) of the Inverter are detailed. The intended study gives a better view and understanding of the applications of energy efficient digital logic of the device at low power.

I. Introduction

Low power circuit implementation using multi-gate MOSFETs have become an important research area due to the increasing demands of the portable application, sensors, bio-medical applications etc. where power dissipation is the pivotal concern instead of speed. Double-Gate Junctionless (DGJLT) MOSFET has gained significant attractions among the multi-gate MOSFETs due to significant improvement in the short channel effects (SCEs) [1]-[2], better Sub-threshold slope (SS) [3], high I_ON/I_OFF, low fabrication complexity etc. So, these DGJLT MOSFETs with low leakage currents, near-ideal sub-threshold slope, and less mobility degradation with temperature and gate voltage [14] can be promising alternatives for the analysis and design of the energy efficient applications.