A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

Source engineering is an emerging technique to achieve steep-slope switching FET. To bridge the new carrier filtering mechanism and device performance, a multiscale simulation framework is presented in this article and is applied in Si nanowire (NW) cold source FET (CSFET). By the fit-parameter-free density functional theory (DFT) method, the key component of cold source (CS) design for broken-gap-like band alignment and high cold carrier injection is demonstrated. The novel device switching mechanism is also verified in the entire device scale with fully quantum atomistic tight-binding (TB) and nonequilibrium Green’s function (NEGF) methods. Although these tools are physics-based and accurate, the device scale is limited, and the computation burden is heavy. Thus, half-empirical TCAD simulation is suitable for device design and path-finding in realistic geometry. Key components of the CS and energy filtering effect can be verified by DFT-NEGF and TB-NEGF methods. Based on TCAD results, we implement a circuit-level benchmark for early stage path-finding. The results show that gate-all-around (GAA) Si NW CSFET is a potential candidate for low-power application, which enables supply voltage scaling.

I. Introduction

To overcome the Boltzmann limit of subthreshold swing (SS) in conventional MOSFET, novel device mechanisms achieving sub-60 mV/dec SS are needed to reduce power dissipation. Recently, cold source (CS) FETs enabled by source engineering have been proposed to suppress carriers in the Boltzmann tail that dominates the subthreshold leakage. CSFET with 2-D material Dirac source has been extensively studied experimentally and theoretically [1]–[6]. Other CS designs include superlattice [7], edge states filter [8], -orbital metal [9], cold metal [10], and broken-gap-like structures [11]–[13]. Among those simulation studies, most proposals are based on accurate first principle simulations. However, the heavy computation burden and limited device scale hinder systematic investigation of device performance. Also, most studies only cover the performance of a single device and lack a circuit-level benchmark for path-finding purposes. On the other hand, TCAD tools are widely used in industry due to the availability of simulating large-scale realistic devices with semiempirical analytic models. However, the accuracy of TCAD simulation depends on calibration and verification.