I. Introduction
To date, several sub-6-GHz CMOS low-noise amplifiers (LNAs) have been reported [1]–[9]. But, the overall performance still has room for improvement. For example, in [3], a sub-6-GHz LNA in 65-nm CMOS is demonstrated. Though low noise figure (NF) of 3.3 dB, of 12.8 dB, and bandwidth (BW) of 19 GHz are attained, its power dissipation () of 20.3 mW is not good enough. For an nMOSFET, instead of connection of its body to source [B-to-, see Fig. 1(a)], its body can be connected to a 5–10- grounded resistor (i.e., B-to- with R). This makes the body floating at RF and equal to 0 at dc. It is useful for insertion-loss reduction in switch applications [10], [11]. Instead of connection of its body to drain [B-to-D, see Fig. 1(b)], its body can be connected to drain through a high resistance [B-to-D with R, see Fig. 1(c)]. This makes the body floating at RF and (equal to ) being forward-biased at dc (i.e., smaller ). is the substrate leakage current in Fig. 2(a). This is the proposed body floating and self-bias technique. From Fig. 2(b), decreases with the increase of , while increases with the increase of due to the decrease of and . To obtain reasonable and low (such as smaller than ), a high (13.6 in this work) can be used. In this work, we report a CMOS LNA using body floating and self-bias technique for sub-6 GHz 5G systems. An enhancement in and NF is achieved. This is because the transistors have smaller due to forward-biased , and are free from (through the ON-resistance of the parasitic body-source diode) due to large [see Fig. 2(c)]. Low power (LP) is achieved since low of 1 or 0.8 V is applicable due to small .
CG input transistor with (a) B-to-, (b) B-to-D, and (c) B-to-D with R.
(a) Circuit diagram and photograph of the LNA. Simulated (b) – and – and (c) – curves of transistor M1.