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3–9-GHz CMOS LNA Using Body Floating and Self-Bias Technique for Sub-6-GHz 5G Communications | IEEE Journals & Magazine | IEEE Xplore

3–9-GHz CMOS LNA Using Body Floating and Self-Bias Technique for Sub-6-GHz 5G Communications


Abstract:

We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 kΩ in this work). A low-pow...Show More

Abstract:

We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 kΩ in this work). A low-power 3-9-GHz CMOS low-noise amplifier (LNA) using the technique for sub-6-GHz 5G systems is reported. An enhancement in S21 and noise figure (NF) of the LNA is achieved due to the forward body-to-source bias ( VBS) (i.e., small threshold voltage Vth) and the transistors being free from the substrate leakage. Low power is achieved since low supply voltage ( VDD) of 1 or 0.8 V is applicable because of small Vth. At VDD of 1 V, the LNA consumes 3.3 mW and achieves prominent S11 of - 10.1 to -41.6 dB, S21 of 10.7 dB, and NF of 2.89 dB for 3-9 GHz. At VDD of 0.8 V, the LNA consumes 1.36 mW and achieves S11 of - 10 to -45.8 dB, S21 of 9.4 dB, and NF of 3.46 dB. To the authors' knowledge, both are one of the lowest power values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and NF under 3.5 dB.
Published in: IEEE Microwave and Wireless Components Letters ( Volume: 31, Issue: 6, June 2021)
Page(s): 608 - 611
Date of Publication: 23 April 2021

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I. Introduction

To date, several sub-6-GHz CMOS low-noise amplifiers (LNAs) have been reported [1]–[9]. But, the overall performance still has room for improvement. For example, in [3], a sub-6-GHz LNA in 65-nm CMOS is demonstrated. Though low noise figure (NF) of 3.3 dB, of 12.8 dB, and bandwidth (BW) of 19 GHz are attained, its power dissipation () of 20.3 mW is not good enough. For an nMOSFET, instead of connection of its body to source [B-to-, see Fig. 1(a)], its body can be connected to a 5–10- grounded resistor (i.e., B-to- with R). This makes the body floating at RF and equal to 0 at dc. It is useful for insertion-loss reduction in switch applications [10], [11]. Instead of connection of its body to drain [B-to-D, see Fig. 1(b)], its body can be connected to drain through a high resistance [B-to-D with R, see Fig. 1(c)]. This makes the body floating at RF and (equal to ) being forward-biased at dc (i.e., smaller ). is the substrate leakage current in Fig. 2(a). This is the proposed body floating and self-bias technique. From Fig. 2(b), decreases with the increase of , while increases with the increase of due to the decrease of and . To obtain reasonable and low (such as smaller than ), a high (13.6 in this work) can be used. In this work, we report a CMOS LNA using body floating and self-bias technique for sub-6 GHz 5G systems. An enhancement in and NF is achieved. This is because the transistors have smaller due to forward-biased , and are free from (through the ON-resistance of the parasitic body-source diode) due to large [see Fig. 2(c)]. Low power (LP) is achieved since low of 1 or 0.8 V is applicable due to small .

CG input transistor with (a) B-to-, (b) B-to-D, and (c) B-to-D with R.

(a) Circuit diagram and photograph of the LNA. Simulated (b) – and – and (c) – curves of transistor M1.

References

References is not available for this document.