Finite Element Analysis of Copper Pillar Interconnect Stress of Flip-chip Chip-Scale Package

Current electronic devices and features sizes are becoming smaller, lighter, with ever-increasing electrical performance requirements. For flip chip devices, Cu-pillar technology enables reduced pitch and reduced package size with good electrical performance. Cu-pillar interconnects require the development of reliable interconnects including many design features such as: die thickness, underfill materials, and substrate design. The enhanced design is needed to avoid issues associated with package warpage, die backside stress, low-k dielectric cracking (during chip attach and temperature cycling), solder joint reliability, and electromigration failure. This paper presents mechanical simulation through finite element modeling of Cu-pillar interconnects and package designs to help the design selection process to improve the reliability of the package under thermal-mechanical loading conditions. The simulation uses a technique of homogenized properties of the Cu-pillar and the underfill material in the die-attach area in the global model to determine stresses. Two failure modes were assessed: a) Brittle fracture of the die and b) Interface delamination between Al pad/die interface. Results show that a thinner Si die has a lower risk of brittle crack compared to the thicker die of 300um. The use of mold compound with higher coefficient of thermal expansion (CTE) reduces delamination risk of the Al pad.

1. Introduction

In the past, the design of electronic packages was done through physically building numerous prototype designs to optimize performance. This approach is time consuming and expensive. A better alternative is to use mechanical modeling through finite element analysis (FEA) to design packages [1]. Today, FEA is widely used in the industry to reduce the number of prototyping activities and accelerate product development [2].