Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator

Recent research shows that an artificial neural network (ANN) can combine multiple heuristics to guide an automatic test pattern generator (ATPG) with fewer backtracks than required by guidance from any single heuristic. Thus motivated, we develop a new training method to include multiple heuristics. Our ANN has a single output neuron and a single layer of hidden neurons, which is sufficient to accommodate the training data volume. Conventional PODEM ATPG applied to hard-to-detect and easily detectable faults in selected benchmark circuits provide training data for nodes marked as “success” if the backtrace leads to a test or “failure” if it results in backtrack. ATPG data of a fault is used for training only if backtracks in the ANN -guided ATPG decrease. Circuit parameters added to training include input-output distances and testability values from COP (controllability and observability program) for signal nodes. Compared to the ANN guidance in previous studies, the proposed training method is found to require fewer total backtracks for all faults in any circuit from ISCAS'85 and ITC'99 benchmarks.

I. Introduction

Automatic test pattern generation (ATPG) belongs in a set of NP-hard problems [1]. Such complexity may force one to try all possible circuit input vectors to find a test for a fault, but this is impractical for large circuits. Popular ATPG algorithms [2], [3] trace backward (i.e., “backtrace”) from an interior node to a primary input (PI) to assign logic values. This action may or may not lead to a test, and in the latter case, the algorithm backtracks, or reverses, the PI assignment. To avoid backtracking, heuristics (i.e., rules based on a designer's intuition) select backtrace directions from available choices.