A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning

Computation-in-memory (CIM) is a feasible method to overcome "Von-Neumann bottleneck" with high throughput and energy efficiency. In this paper, we proposed a 1Mb Multi-Level (MLC) NOR Flash based CIM (MLFlash- CIM) structure with 40nm technology node. A multi-bit readout circuit was proposed to realize adaptive quantization, which comprises a current interface circuit, a multi-level analog shift amplifier (AS-Amp) and an 8-bit SAR-ADC. When applied to a modified VGG-16 Network with 16 layers, the proposed MLFlash-CIM can achieve 92.73% inference accuracy under CIFAR-10 dataset. This CIM structure also achieved a peak throughput of 3.277 TOPS and an energy efficiency of 35.6 TOPS/W with 4-bit multiplication and accumulation (MAC) operations.

I. Introduction

With the rapid development of artificial intelligence (AI) algorithm, the research and application of convolutional neural network (CNN) has become more and more extensive. However, in conventional Von-Neumann architecture, memories and computing units are connected with limited bus. The frequent transfer of data between memories and computing units will generate huge energy consumption. This severely limits the development of convolutional neural networks, which has large amounts of data and high computational density [1]. In order to overcome the above limitations, the architecture of Computation-in-Memory (CIM) was proposed and became a promising field both in the academia and industry [2]-[6]. CIM architecture embeds the computing circuits in the memory, therefore, it can perform some calculations in the memory while serving as an ordinary memory. Computation in memory will greatly reduce the data migration, the energy consumption of accessing memory and increases the calculation speed [2]-[14]. And CIM architecture is considered to be one of the mainstream trends of artificial intelligence algorithm hardware acceleration in the future.