Static Timing Analysis of Sequential Circuit with GUI

The Static time analysis (STA) used to verify the timing satisfiability of the sequential digital circuit. The occurrence of data input must synchronize with the active edge of the clock else metastable error results. A dedicated tool required to analyze the timing issue; Primetime by Synopsis. The main goal of this work is to design an STA solver with open-source technology. The methodology of computation has been implemented in Tcl (tool command language) and graphical user interface (GUI) has been implemented with the toolkit (Tk) comprises of an interactive visual component. GUI provides a simple way to interact with the system and make the analysis easy to understand; while existing tool are based on hardware programming language. The user has to provide input as data and clock frequency, GUI returns the positive and negative slack up to 5-clock edges and indicate whether the metastable state error occurs or not. The presented GUI computes the slack (reserve time between and after the required time of clock and arrival time data). A binary executable file of the STA solver verifies the setup and hold timing errors.

I. Introduction

Static time analysis (STA) is a critical timing analysis of the sequential circuit, ensures clock and data input of the sequential circuit must be synchronized. A stable value of data input must apply on the active edge of the clock than only it gets recognized [1]. To faithful output at the flip flop (FF) Q terminal, data must maintain constant for the timing window justified by setup and hold time of flip flop (FF) demonstrated in [2]–[4]. Setup and hold time are measure before and after the active edge of the clock respectively. Practically setup time, minimum time required by a FF to read data from the input terminal, and hold time is the minimum time required by FF to write data over the Q terminal. During this process, if data change results in invalid results presented by don’t care (X-state); known as metastable error. Thus, it is necessary that period of data input adjusted without violating the setup – hold requirement at every edge. A mathematical computation model in [1]–[5] measure the arrival time of data and the required time of the clock on the active edge of the clock. Need of graphical tool highlighted in [6], [7] indicates users prefers to perform computation with graphical interface rather than standard input/output methodology. In this work a GUI of the static time analysis is presented can compute the timing violation till 5-edges of a clock with Tcl-Tk. A GUI system consists of an interactive visual component. GUI provides a simple way to interact with the system. It processes the user’s information and displays results. The combination of a different color, size makes the interface more attractive. Nowadays simulation tool is coming up with its own GUI interface towards education 4.0 [8]. The efficiency and usability of the tool are described by the better interactive. In this paper the process of GUI development by Tcl (Tool command language) extension Tk (Toolkit) presented. Tk creates the interactive interface using widgets where the user types the input , commands and parameter to the execution of the Tcl program in the background and provides a solution to view the result [9]–[12]. It eliminates the maximum typing and makes the interface more attractive. The developed STA solver computes the setup slack and holds slack up to 5-clock edges, where slack is defined as the difference of required time by the clock to the arrival time of data. The positive value of slack says no violation while the negative value of slack identifies particular timing constraints violated.