Enhancement-mode power heterojunction FET utilizing Al/sub 0.5/Ga/sub 0.5/As barrier layer with negligible operation gate current for digital cellular phones

We have developed a novel enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET (HJFET) with a 5 nm thick Al/sub 0.5/Ga/sub 0.5/As barrier layer inserted between an In/sub 0.2/Ga/sub 0.8/As channel layer and an upper Al/sub 0.2/Ga/sub 0.8/As electron supply layer. The Al/sub 0.5/Ga/sub 0.5/As barrier layer reduces gate current under high forward gate bias voltage, resulting in a high forward gate turn-on voltage (V/sub F/) of 0.87 V, which is 170 mV higher than that of an HJFET without the barrier layer. Suppression of gate current assisted by a parallel conduction path in the upper electron supply layer was found to be also important for achieving the high V/sub F/. The developed device exhibited a high maximum drain current of 300 mA/mm with a threshold voltage of 0.17 V. A 950 MHz PDC power performance was evaluated under single 3.5 V operation. An HJFET with a 0.5 /spl mu/m long gate exhibited 0.92 W output power and 63.6% power-added efficiency with 0.08 mA gate current (I/sub g/) at -48 dBc adjacent channel leakage power at 50 kHz off-center frequency. This I/sub g/ is one-thirteenth to that of the HJFET without the barrier layer. These results indicate that the developed enhancement-mode HJFET is suitable for single low voltage operation power applications.

I. Introduction

Recently, power devices which can be operated with a single voltage are in great demand for cellular applications. For the demand, an enhancement-mode heterojunction FET (HJFET) which showed excellent power performance is a probable candidate [1], [2]. For the FET, a negligible drain leakage current () at a gate-to-source voltage () of 0.0 V is desirable, because the drain bias switch can be eliminated, thus realizing low cost and small size cellular phones. In order to realize a negligible , a positive threshold voltage () of more than 0.2 V is necessary for about a 1 W class power FET with a gate width () of more than 20 mm [3] [4]– [6]. With an increase in close to forward gate turn-on voltage (), however, forward gate current () under power operation increases due to a decrease in gate voltage swing margin. This degrades power performance of the enhancement-mode FET, therefore increasing becomes the key issue.