Physical Bridge Design for High Performance to Peripheral Bus: An Open Source Approach | IEEE Conference Publication | IEEE Xplore

Physical Bridge Design for High Performance to Peripheral Bus: An Open Source Approach


Abstract:

The Advanced Microcontroller Bus Architecture (AMBA) offering from ARM is one of the most widely used standards for System on Chip (SoC) design in the semiconductor indus...Show More

Abstract:

The Advanced Microcontroller Bus Architecture (AMBA) offering from ARM is one of the most widely used standards for System on Chip (SoC) design in the semiconductor industry. The specifications defined by AMBA provide many advantages such as right-first-time development and technology independence for design of high performance chipsets. The main focus in this paper is on two protocols - Advanced Highperformance Bus (AHB) and Advanced peripheral Bus (APB). Keeping in mind that these specifications are an open standard, we aim to develop an AMBA AHB-APB bridge from Register Transfer Level (RTL) to Graphical Display System (GDSII) using only open source tools and libraries. The proposed design is developed with Verilog Hardware Definition Language (HDL), followed by compilation and functional simulation. Physical design is performed after verification to obtain graphical display of the bridge module. Detailed analysis of the results obtained indicates that open source options are viable to test various digital designs obviating the need to invest in expensive proprietary design tools. This would accrue benefit by greatly improving the scope and reach of Very Large Scale Integration (VLSI) design.
Date of Conference: 11-12 December 2020
Date Added to IEEE Xplore: 05 February 2021
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Conference Location: Bengaluru, India
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I. Introduction

The AMBA specification, provided by ARM, is an open interconnect standard for high performance SoC designs in the semiconductor industry. With exponential improvements in fabrication technology and reducing feature size of MOSFETs, these specifications were designed in order to satisfy four key requirements [1]:

• To enable right-first-time development, thus reducing costs

• To be technology independent, so that cells once designed can be reused

• To encourage modular system design to reduce repeatability, thus improving design time

• To reduce amount of silicon used for on-chip and off-chip communication

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