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Reconfigurable PETPG for External Testing of Digital Circuits | IEEE Conference Publication | IEEE Xplore

Reconfigurable PETPG for External Testing of Digital Circuits


Abstract:

In this paper, the application of the board-level external testing using the pseudo-exhaustive testing (PET) was explored. The new design approach to reconFigure the hard...Show More

Abstract:

In this paper, the application of the board-level external testing using the pseudo-exhaustive testing (PET) was explored. The new design approach to reconFigure the hardware of the pseudo-exhaustive test pattern generator (PETPG), based on the permutated convolved linear feedback shift register/shift register (LFSR/SR), is developed. The permutated convolved LFSR/SR is considered a superset of all previously published output-specific PETPGs in the PET with low test application time (TAT). The PET segments digital circuit-under-test (CUT) into several output cones. The proposed test system can stimulate all combinational hard faults in each output cone using the reconfigured PETPG without the need of the fault simulator, and to compact test responses of digital circuits for signature generation. The simulation results using some digital circuits, compared to previously published works, illustrate the effectiveness of the presented test approach to detect target faults with reduction of TAT.
Date of Conference: 15-16 December 2020
Date Added to IEEE Xplore: 01 February 2021
ISBN Information:
Conference Location: Cairo, Egypt

I. Introduction

Number of automatic test systems are available, the variations are extensive, but most of them fall into two main categories; functional tester (FT) and in-circuit tester (ICT) [1–8]. The ICT individually examines each component on a board and requires an expensive test-fixture. However, the FT verifies the functions of a board designed for. Only board inputs and outputs need to be tested with simple test-fixture. Therefore, this paper deals with the FT, considered an important issue in industrial applications. In addition, there are two main categories of fault models in digital circuits; static and dynamic faults. Static faults are detected by single-pattern test vectors [7–9], and dynamic faults or only-at-speed fault models are detected by two-pattern test vectors [10].

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References

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