CMOS IC Design from Schematic Level to Silicon within IC Curricula Using Free CAD Software

In this paper we demonstrate the free and open-source methodology used to design integrated circuits all the way from schematic level simulation to silicon-ready GDS fabrication files. This approach has been successfully implemented in the IC design curricula at the Faculty of Electrical Engineering, University of Banja Luka. The example circuits are known designs of a low-dropout regulator and an oscillator. The CMOS technology node is 180 nm process. Each of the tools is briefly presented, and either of the two designs is shown during different design phases.

I. Introduction

Fabrication of monolithic integrated circuits (IC or chip) on silicon represents one of five technologies crucial to semiconductor industry and, therefore, human society in this, 21^st, century [1]. Even though its performance rise due to constant scaling has been significantly slowed down in comparison to the previous half a century, it is still one of the most sophisticated technology processes commercially available in the world. This came to pass due to incredible scale of integration, which, in return, allowed mass IC production at negligible price per unit produced. Nevertheless, contrary to the end product unit price, as low as several cents for the most common chips, the cost of design, fabrication, packaging and testing of an IC has been soaring all along. It is first very costly to train an engineer, then it costs hundreds of thousands to obtain a yearly license of an industry standard software toolchain, whereas fabrication in the modern process node may cost well into millions. Verification usually takes up to 30% of the whole project cost.