Introduction
For growing demands of 3D stacked chips with high density and communication speed, such as CMOS image sensor (CIS) and high bandwidth memory (HBM), hybrid bonding (Fig. 1a) with lower communication loss and shorter connection length is a preferred technology, comparing to copper pillar with solder joint [1] (Fig. 1 b). However, for reliable Cu-Cu contacts, conventional hybrid bonding requires additional surface pretreatment steps and high annealing temperature (350–400 °C) [2]–[4]. In this work, a low temperature CU/SiO2 direct hybrid bonding process has been demonstrated by using the metal passivation layer, which provides more product realization options with 3D integration. Bonding schematic and real chip demonstration are shown in Fig. 2.