A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

This paper describes a 1.0 Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m-CMOS HSPICE simulation. The circuit is under fabrication. The measured results are presented.

1. Introduction

Modern data communication systems make it difficult to design high speed CMOS clock and data recovery circuits. To overcome this difficulty, an oversampling CMOS clock and data recovery (CDR) circuit that requires high-speed multi-phase clocks and ability to detect phase and frequency variation of input data at the same time was proposed[1]. However. the oversampling CDR circuit requires relatively larger area and larger power consumption. Another high speed CMOS CDR circuit uses a phase frequency detector(PFD) composed of complex state machines and VCO[2]. Also, various types of PFD such as a conventional PFD[3] or dynamic PFD[4], [5] were used to build high speed CMOS CDR circuits.