SMPS electromagnetic noise in System-on-Chip: Noise propagation

There is a trend for embedding of a power management unit along with digital system-on-chip. Few off-chip passive components are necessary. The embedded power management unit is meant to deliver dynamical adequate voltage levels to improve the performances of the mix-mode system. The conversion architecture is optimized in efficiency against high and low power mode but preventing impacts on the analog performance of sensitive blocks in the mix-mode system. The active part of an inductive buck converter is integrated but some switching noise is observed that severely impact analog blocks. The objective of this work is the analysis of the noise propagation of the SMPS noise in the SoC part. The whole system, i.e. the electronic board holding the package and the SoC-chip, is modeled to extract the system-level propagation paths between the buck converter and sensitive blocks. The analysis of the model permits to discriminate the different propagation paths inside the chip through the silicon substrate or outside by PCB interconnection and ground plane. The model is verified by measurement on a test vehicle.

I. Introduction

The objective is to understand how the noise generated by a buck converter inside a SoC is propagating to the affected sensitive IP of the same chip. The source of this noise, the power stage switching and the associated resonance frequencies were shortly described in a previous paper [1]. There are two steps to analyse the propagation of this noise. First the entire system is modeled and compared to measurement to verify that all paths have been considered. Second the parameters of the model are modulated to evaluate which of the propagation paths are predominant.