Loading [MathJax]/extensions/MathZoom.js
Moore and Mealy Negative Edge detector A VHDL Example for Finite State Machine | IEEE Conference Publication | IEEE Xplore

Moore and Mealy Negative Edge detector A VHDL Example for Finite State Machine


Abstract:

In modern societies we are more dependent on computerized tools, they help us to cope with recent modern lives. The automatic machines perform a variety of operations by ...Show More

Abstract:

In modern societies we are more dependent on computerized tools, they help us to cope with recent modern lives. The automatic machines perform a variety of operations by adapting the changes in the physical environment. Here in this two varieties FSM, Moore and Mealy, are mentioned. Moore and Mealy machine state diagram are designed and implemented by using a negative edge detector circuit. The designed state machines are implemented in VHDL. For both state machines comparison is also made.
Date of Conference: 28-30 July 2020
Date Added to IEEE Xplore: 01 September 2020
ISBN Information:
Conference Location: Chennai, India

I. Introduction

SM is which changes from one state to another state due to applied external inputs. The change from one state to another state is called a transition. An FSM is defined by a list of its states, it has its initial state, and final state for each input [1–6]. Fig. 1 illustrates the working of a FSM model. Usually it has bubble and arrow in the diagram [7, 8]. The bubble indicates the state and an arrow indicates the direction from state to state [9]. The state machine has present state and next state when the clock signal is applied [10–12].

References

References is not available for this document.