Abstract:
The errorless data transmission in optimal communication depends on flaw identification and renewal techniques. In one bit error identification and error modification cod...Show MoreMetadata
Abstract:
The errorless data transmission in optimal communication depends on flaw identification and renewal techniques. In one bit error identification and error modification codes the hamming code is mostly used, because of its efficiency. To increase performance, system capability we need the low power design. To reduce the rate of information loss and power dissipation the reversible logic is well suited. When a reversible logic gates used in the design of hamming code, in place of irreversible logic gates gives low power dissipation, which identify and modify the error if any. In this document we construct the hamming code using the FinFET technique, because of its capability of operating at lower supply voltages and it is suppress the short channel effects in sub-micron region, through this documentation we represent the propagation delay values. The transient responses are taken by using cadence virtuoso. The power consumption of overall design is 0.48□W.
Date of Conference: 28-30 July 2020
Date Added to IEEE Xplore: 01 September 2020
ISBN Information: