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New Double Fault Tolerant Full Adder Design for Real-Time Applications | IEEE Conference Publication | IEEE Xplore

New Double Fault Tolerant Full Adder Design for Real-Time Applications


Abstract:

Using VLSI more number of transistors can be embedded on a single chip. As the space between transistors or circuits decreasing the system or chip is more susceptible to ...Show More

Abstract:

Using VLSI more number of transistors can be embedded on a single chip. As the space between transistors or circuits decreasing the system or chip is more susceptible to faults. Fault tolerant systems required to avoid inaccurate results. Full adder is basic building block for addition of multi bit numbers. The existing structure proposed is unable to detect fault in sum for some combinations. The proposed design can detect concurrent faults in both sum and carry. And also the proposed structure can repair the faults itself. This self repairing full adder structure can detect and repair the single and multiple faults. The proposed structure gives 100% error recovery. The circuit is simulated using Cadence tool and verified the functionality.
Date of Conference: 28-30 July 2020
Date Added to IEEE Xplore: 01 September 2020
ISBN Information:
Conference Location: Chennai, India

References

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