Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.

I. Introduction

Through technology development, applications are becoming larger, which may create some problems, such as shortage of resources and long implementation time, especially in the placement and routing steps when they are implemented for hardware devices. In this regard, using dynamic partial reconfiguration (DPR), which is available in some of the new advanced field-programmable gate arrays (FPGAs), is regarded as a solution to eliminate this problem. Regarding FPGAs with DPR capability, placing nonsimultaneous modules on the same region of FPGA is possible in a time-multiplexed way. In addition, there are some advantages for utilizing DPR capabilities, such as the reduction in FPGA size, as well as power and cost, algorithms with more flexibility in applications, newer techniques for project security, and greater fault tolerance in FPGAs. Furthermore, there are some new projects that are impossible for implementation without DPR [1]. Vipin and Fahmy [2] provided comprehensive reviews of the methods and applications of DPR FPGAs. There are several methods for designing systems with DPR capability. This article aimed to design a modular design method called “partitioning” [3]. As shown in Fig. 1, a sample of a DPR-enabled system is available against a full-static implementation. The green region shows the location of the static modules (modules that are presented on the FPGA from the beginning to the end of the process), and the reconfigurable modules are in the blue and red regions. When the program runs, the modules in the green region are fixed, but there is at most one of the modules specific to their region in each of the blue and red zones at any time. System functionality changes by replacing the red or blue modules. Fig. 1.

DPR implementation (left) and full-static implementation (right).