Low Latency and Area Efficient Very Large Scale Integration Architecture of 2-Dimensional Bicubic Interpolation using Carry Save Adder Based Fast Multiplier

Presently, real-time image processing is gaining increasing popularity, specifically in the field of satellite imaging and medical imaging. Naturally, researchers are increasingly being inclined to design dedicated hardware for imaging methods to aid real-time processing in a cost-effective way. Likewise, several VLSI architectures have already been designed for a variety of imaging methods. But, in spite of being a significant and popular imaging method, the image interpolation has no such notable dedicated VLSI architecture so far. Image interpolation has vast applicability ranging from image inpainting to image registration. In all such applications, the image interpolation part has been performed by software-based implementations. To alleviate the issue, a dedicated VLSI architecture 2D bicubic interpolation has been designed. The proposed bicubic architecture is based on state-of-the-art VLSI architectures for performing square and cube operations following vedic mathematics. Furthermore, all the adders used in the proposed design are judiciously developed to increase the speed retaining an acceptable area and power consumption. The proposed architecture is realized in the xilinx vivado 18.2 tool. The simulation results exhibit satisfactory performances. The quality of the proposed bicubic architecture has also been successfully tested by on board testing using the xilinx ZCU104 board to verify the viability of the design to be applied in real-time imaging applications.

I. Introduction

Bicubic interpolation is one of the efficient methods to find unknown pixels in digital image processing. In recent days many researchers have tried to improve the algorithm to improve image quality. They have come up with new ideas that have helped a lot to find unknown pixels value. But at one place existing ideas are lagging. Till now, researchers have tried to improve image quality only in software level using a local machine. There is no harm in doing it in a local machine with the help of software, but the time and process complexity also increase. So, in this paper, our main interest is to overcome this deficiency by implementing the process of reconstruction of image with the help of hardware that leads to an on-chip image reconstruction architecture using the help of a bicubic interpolation technique. The bicubic technique is used whenever there is a necessity to transform LRI (Low-Resolution Image) to HRI (HighResolution Image) or to store the old images or to scale up or scale down the image pixels. The proposed architecture is successfully verified using on board testing and that can be fabricated on-chip for real-time image processing. This architecture will compete with software-intensive processes that are present in the market. In the next subsequent sections, it can be observed that our architecture will do the same task in an efficient manner in terms of latency, throughput, and the number of a clock cycle.