Contents I. Introduction
The III-V compound semiconductor nanowires (NWs) are promising alternative channel materials for high-performance and low-power field-effect transistors (FETs) due to their high electron mobility and vertical gate-all-around (VGAA) structures [1]–[11]. Among the III-V channels, InAs channels have a much higher electron mobility. However, this channel material has a problem regarding large off-state leakage current due to the narrow band gap with a small electron effective mass. Moreover, InAs contains a large concentration of donor-type surface states resulting in reduced electron mobilities [11]. The core-shell (CS) structure, in which the core NW is surrounded by radial heterostructure, would provide the confinement carriers inside the core NW and would enhance the carrier mobility due to suppression of the carrier scattering process [11]–[13]. Another benefit of the CS structure is surface passivation [14]. Recently, we demonstrated an InAs NW-channel for VGAA FET on Si [15], [16], and achieved small subthreshold slope (SS) and off-leakage current. However, the challenge in obtaining a high on-state current for the InAs NWs directly integrated on Si remains. In this letter, we investigated InAs/InP core-shell NW-channels to confine carriers in the core NW.
