A 37–40-GHz Low-Phase-Imbalance CMOS Attenuator With Tail-Capacitor Compensation Technique

A Ka-band 5-bit CMOS digital step attenuator (DSA) with low phase variations for 5G applications is presented. The attenuator cell is optimized to alleviate the phase variations of conventional switched attenuators. A tail capacitor that is connected in series with the shunt resistor is used to construct a correction network with hyperbolic function characteristics. The DSA was implemented using a 65 nm CMOS process. It has a maximum attenuation range of 31 dB with 1.0 dB steps. With the help of the tail capacitor, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.27 dB and a rms phase error less than 3.7° from 37–40 GHz, the lowest such errors ever reported. The active core layout area is 0.22 mm² (0.51 mm $\times \,\, 0.42$ mm). It shows suitable performance for 5G applications. The DSA is integrated into a phase-/amplitude-controlling chip to constitute a 5G system.

I. Introduction

With the fast development of wireless technology, research on millimeter-wave technology for 5G applications has become popular [1], [2]. To meet the high data transmission rate requirements for 5G communication systems, a millimeter-wave communication system should have the ability to realize beam forming and scanning [3]. Therefore, millimeter-wave phased array systems are considered as the next-generation communication systems. Due to its multiple channels, a phased array system requires low direct current power consumption, low production cost and high integration density for each channel [4]. Benefiting from the continued scaling of deep-submicron CMOS technology, the integration density of silicon-based circuits is increased, the circuit power consumption is reduced and the cut-off frequency () is increased [5]. Thus, this technology has emerged as a competitor to the gallium arsenide (GaAs) process for microwave front-end applications.