A low complexity FPGA implementation of uplink SCMA decoder

Sparse code multiple access (SCMA) is a novel non- orthogonal multiple access (NOMA) scheme to face 5G communication, adopting message passing algorithm (MPA) to demodulate users’ message in the receiver. When LOG-MPA transfers MPA into log-domain, the expansion contains correction term suffering complicated calculation. In that case, a FPGA implementation Scheme is proposed on the basis of Maclaurin series, which retains correction term and has fewer iterations. The Simulation results show that proposed scheme can obtain closed BER performance to LOG-MPA, while possessing a lower complexity. Finally, FPGA verification on Vivado HDL platform proves the design has complete function and can be applied in practice.

I. Introduction

Multiple access is a key technology for future wireless communication, which provides an excellent system solution when there are many users. Sparse Code Multiple Access (SCMA) is a new non-orthogonal multiple access (NOMA) technology proposed in 5G. The key to SCMA technology is the sparse codebook designed for each user at the transmitter, the data sent by each user will be encoded by the codebook and then superimposed on the resource block. At the receiver, in order to demodulate data of different users, an appropriate multi-user detection (MUD) is needed, and the message passing algorithm (MPA) based on factor graph iteration ^[1] becomes the best choice. The original MPA algorithm has high computational complexity, in addition too much multiply and exponentiation are required, which limits the application in hardware. Therefore, optimizing the receiver detection algorithm has become an important topic in SCMA study.