Contents I. Introduction
Quantum technology has made remarkable progress in the last two decades [1]. Among quantum technology’s four main areas—which also include communication, simulation, and sensing and metrology—quantum computation is gaining particular relevance. In this respect, increasing interest has been recently directed to the possibility of using through-silicon vias (TSVs) at cryogenic temperatures [2]. Such interest was boosted by the demonstration of silicon-based quantum computers, which need to operate at temperatures lower than 1 K [3]. The quest for superconducting vias arises from the realization that the number of physical qubits required for the control and error-correction of logical qubits is nowadays a limitation to compete with the performance of classical computers [1]. Actually, several millions of physical qubits should be integrated on an single chip to achieve substantially higher performance [4]. Current implementations of superconducting and spin qubits in silicon require an area orders of magnitude larger than the size of typical MOS transistors [3]. This severely limits qubit integration density in a single substrate. High qubit integration densities therefore require multilayer technologies, and 3D superconducting interconnects may suit the purpose (Fig. 1): they allow to get rid of interconnecting wires, freeing chip surface to increase qubit density, as well as to vertically stack and interconnect multiple chips [5].
Sketch of the proposed 3D integration concept for large-scale high-density quantum computing, including a qubit-based layer, TSV-based superconducting interconnects in an interposer layer, and the CMOS circuitry for the control and readout of the qubits.
