Interference Analysis of Multicore Shared Resources with a Commercial Avionics RTOS

Commercial off-the-shelf (COTS) multicore architectures are being deployed in avionics systems. However, the shared resources of multicore architectures cause inter-core interference (ICI). This interference degrades the predictability of the execution time of avionics systems. To reduce interference, a regulator of operating system (OS) that restricts resource usage per core has been proposed. Due to the nature of avionics systems, modifying OS or software poses problems with safety verification and certification. In this paper, we analyzed the ICI due to shared memory in COTS hardware. Furthermore, we analyzed the impact of interference improvement through Time Division Multiple Access (TDMA) and Acquisition-Execution-Restitution (AER) execution models proposed in previous studies. The execution model can reduce interference without modification of the code. However, previous studies have analyzed the interference using an OS-less environment or a non-commercial OS. Hence the OS overhead is not considered. This paper analyzes the shared resource interference in commercial OS based on ARINC 653. We also propose a method for implementing an execution model in the OS. Through experiments, we show that interference by shared resources is reduced by applying TDMA and AER models. In the case of TDMA, execution time is reduced by up to 10%. The AER model has increased execution time due to the control of the execution flow among the cores, but it has been possible to reduce the major cycle by increasing the utilization. The variation of cache misses is reduced through TDMA and AER execution models. The number of occurrences also decreased by about 10%.

I. Introduction

As the computing power requirements of avionics systems grow, multicore architectures are being introduced. Especially in safety-critical environments such as avionics, asymmetric multiprocessing (AMP) has been adopted to ensure robustness [1]. AMP can reduce interference between cores because each core is operated independently. However, commercial off-the-shelf (COTS) hardware does not separate hardware resources per core, so multiple cores share the same hardware resources. In COTS hardware, even when AMP is used, inter-core interference (ICI) due to shared resource occurs. ICI makes the execution time in the avionics system nondeterministic.