A Cascaded Multi-Drive Stacked-SOI Distributed Power Amplifier With 23.5 dBm Peak Output Power and Over 4.5-THz GBW

This article presents a cascaded distributed power amplifier (DPA) topology with greater than 4.5-THz gain-bandwidth (GBW) product. The DPA uses stacking with multi-drive inter-stack coupling to compensate for the stacked gain cells and input transmission-line (TL) losses. The techniques improve the gain and output power without compromising the bandwidth (BW). The cascaded DPA employs eight-shaped TLs to allow inter-stack coupling in a compact area and for field confinement. A 33-dB gain, 101.5 GHz BW DPA is realized in the 45-nm RFSOI GlobalFoundries process. The amplifier maintains P_1dB and P_SAT > 18.7 and 21 dBm, respectively, up to 60 GHz, with over 60 GHz P_SAT 3-dB BW, while demonstrating >14 dBm of average P_OUT for a 30-Gb/s 64-QAM modulated signal, with an error vector magnitude (EVM) <; 5%. The DPA is also able to provide a 72-Gb/s 64-QAM signal with 13.6 dBm average P_OUT from a 13 GHz carrier frequency. To the best of our knowledge, the cascaded multi-drive DPA achieves the highest reported GBW, continuous-wave (CW) P_SAT, and average P_OUT for 64-QAM 30-Gb/s modulated signal, in a compact core area compared to published silicon-based DPAs with comparable power levels.

I. Introduction

With the emergence of millimeter-wave (mm-wave) technologies, the ability of distributed power amplifiers (DPAs) to achieve high output power (), large gain and wide bandwidth (BW), in commercial CMOS technologies will open the door to new broadband applications. There is, however, a design tradeoff, where most of reported silicon-based distributed amplifiers (DAs) either have a GHz in exchange with low-power performance [1]–[6], or an output power >15 dBm with a smaller BW [7]–[13]. The reason is that high-power generation under a limited voltage supply requires large device sizes for high-current generation (low-impedance designs). However, in DAs, a high is achieved by increasing the number of stages while keeping a small device per stage to preserve the BW. The number of stages is limited by the input transmission-line (TL) loss that increases with frequency, as higher TL loss impedes the input signal flow to the last stages, limiting their and gain contribution. The gain–bandwidth (GBW) product can still be improved for a limited by cascading DAs to increase the gain at the expense of chip area and efficiency.