25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing

This work presents a fully integrated PSN analyzer with significantly improved measurement speed and noise performance. Compressed sensing is exploited due to the sparse nature of PSN signals. A VCO-based muiti-level phase quantizer is proposed, offering improved noise performance. A polyphase clock generator is also implemented on chip, enabling the whole system to work with only one external clock reference. Under a BW of 20GHz, the proposed PSN analyzer is 200x faster with 5x higher frequency resolution and a 42x lower noise floor as compared to the previous work.

Power-supply noise (PSN) is a key consideration that determines the performance, as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration, and sophisticated voltage and power controls. Externally measured PSN is inevitably distorted by packaging and other factors; therefore, on-die measurement of PSN is highly desirable with large bandwidth, high accuracy, high frequency resolution and reasonable measurement time, which are extremely challenging to achieve design objectives. A sample/hold-based approach with direct voltage comparison provides limited resolution under noisy supplies, preventing it from spectral measurement [1]. Time-domain comparison with VCO-based quantizers have been proposed with improved resolution and scalability. However, the fundamental tradeoff between bandwidth and accuracy has limited the high-frequency performance of S/H-based measurements, with bandwidth often limited to 10GHz [2]. Subsampling-and-averaging-based approaches relax the bandwidth constraints, often requiring PSN-uncorrelated sampling clocks [3]. In addition, the accuracy and frequency resolution of averaging-based measurements are fundamentally determined by the number of measurement points, resulting in lengthy measurement time, e.g. taking tens of minutes to achieve 20GHz BW with 10MHz frequency resolution [4].