Interconnect synthesis without wire tapering

Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This paper studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering for signal nets. Finally, we present a general formulation and optimal polynomial time algorithm for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing.

1. Introduction

The Scaling of process technology into the deep submicron regime has made interconnect performance more dominant than transistor and logic performance. With the continued scaling of process technology, resistance per unit length of the interconnect continues to increase, capacitance per unit length remains roughly constant, and transistor or logic delay continues to decrease. This trend has led to the increasing dominance of interconnect delay over logic delay. Process technology options, such as use of copper wires, can only provide temporary relief. The trend of increasing interconnect dominance is expected to continue. The timing optimization techniques of wire sizing and buffer insertion/sizing have gained widespread acceptance in deep submicron design (see Cong et al. [11] for a survey).