Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on low-frequency noise (LFN) was carried out for the commercial 1.2-kV/30-A silicon carbide (SiC) power MOSFETs under repetitive short-circuit (SC) stress. The experiment results show that the on-state resistance (R_dson) and threshold voltage (V_th) increase significantly. Meanwhile, the drain-source current (I_ds) decreases obviously with the increase of the SC cycles. Furthermore, the gatesource leakage current (I_gss) of the SiC power MOSFETs increase greatly and the blocking characteristics deteriorated after 1000 SC cycles. The positive shift was observed on the gate-capacitance versus gatevoltage (C_g-V_g) curve, which shows that the damage region could be in channel along the SiC/SiO₂ interface after repetitive SC stress. In order to obtain the trap information, trap characterization was performed by using LFN method, and the LFN results show that the trap density increases with the SC cycles. The physical mechanism could be attributed to electrically active traps generated at SiC/SiO₂ interface and oxide layer due to the peak ionization rate, the perpendicular electrical field and high temperature during SC stress. The study may be useful to provide reference for converters design and fault protection of SiC power MOSFETs.

SECTION I. Introduction

Silicon carbide (SiC) material has been recognized as a prime option for increasing the power density, system switching frequency and system efficiency of power electronics due to its superior properties [1]–​[3]. In recent twenty years, SiC MOSFETs have been widely applied in power electronics device with the rapid improvement of material fabrication technology [4]. However, in most applications, SiC power MOSFETs can suffer from extreme operating conditions that result in degradation, such as low channel mobility [5], poor reliability [6] and so on. Therefore, it is important to explore the reliability of SiC power MOSFETs.

Power semiconductor devices are expected to function for short amount of times outside their designed safe-operating area without any impact on the device performance. Among of them, short-circuit (SC) operation is inevitable, and the SC capability is a crucial indicator of SiC power MOSFETs reliability [7]. Recently, some papers have been dedicated to the SC behavior of SiC power MOSFETs. The electrical properties of 1.2-kV/10-A SiC power MOSFETs under repetitive SC stress were reported, and the dominant mechanism was attributed to negative charges generated along the SiC/SiO2 interface of the channel region [8]. The robustness and electro-thermal instability of 1.2-kV SiC power MOSFETs were investigated under the SC stress, and it was found that the gate was weakness [9], [10]. Under repetitive 6-kV dc-link voltage stress, the on-state resistance (${R} _{\mathrm{ dson}}$ ) increases significantly for the 10-kV/10-A 4H-SiC MOSFET [11]. There are also reports on the comprehensive SC ruggedness evaluation and numerical investigation of 1.2-kV SiC MOSFETs [12]. The gradual reduction on the gate-source voltage (${V} _{\mathrm{ gs}}$ ) in SiC power MOSFETs was investigated during SC condition, which results in the increases of gate-source leakage current (${I} _{\mathrm{ gss}}$ ) due to the smaller thicknesses of the gate oxide [13].

Low frequency noise (LFN) measurements are presented to be a powerful tool to evaluate the quality and reliability of Si and SiC based MOS transistor [14]–​[16]. LFN of Si MOSFETs has been extensively studied [17]. The temperature-dependent LFN of 4H-SiC MOSFETs with nitride oxides was reported over the temperature range 85–510 K, and the 1/${f}$ noise decreases significantly with increasing measurement temperature [18]. LFN in 4H-SiC JFETs has been investigated, and these extremely low noise values were determined by the noise at the SiC/SiO₂ interface [19]. The 1/${f}$ noise in 4H-SiC MOSFETs with epitaxial channel has been investigated, and it was shown that the density of negative oxide traps are responsible for 1/${f}$ noise [20]. The bulk LFN has been investigated on the 4H-SiC polytype, and in the temperature range of 300–550 K the noise spectral density ${S}$ is proportional to 1/${f} ^{1.5}$ [21]. The noise power spectra for n-channel, depletion-mode MOSFETs fabricated in 6H-SiC material was measured from 1 Hz to 100 kHz at room temperature and the noise power spectra were found to be dependent upon the drain-source current (${I} _{\mathrm{ ds}}$ ) density [22]. The LFN was studied in 4H-SiC MOSFETs in the frequency range from 1 Hz to 100 kHz, and the dependence of the normalized noise power spectra (${S} _{I}/{I} _{\mathrm{ ds}} ^{2}$ ) on ${I} _{\mathrm{ ds}}$ at constant drain-source voltage (${V} _{\mathrm{ ds}}$ ) was qualitatively different from typical dependence for n-channel Si MOSFETs [23]. However, to our best knowledge, very limited research efforts have been focused on the degradation analysis and physical mechanism of SiC power MOSFETs based on LFN measurements.

In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on LFN was carried out for the commercial 1.2-kV/30-A SiC power MOSFETs under repetitive SC stress. The effect of repetitive SC stress on the gate oxide and body diode were explored. The corresponding physical mechanism for the effect of traps increasing after repetitive SC stress was also discussed. The results may provide useful reference for converters design and fault protection of SiC power MOSFETs.

SECTION II. Experimental

A commercial 1.2-kV/30-A SiC power MOSFET produced by Wolfspeed (C3M0075120K) was chosen as the target device. The schematic diagram of cross section and photograph of the typical device under test (DUT) was shown in Fig. 1. The electrical characteristics were measured by semiconductor device analyzer (Agilent B1505A). And LFN was measured by using SR785 dynamic signal analyzer, while filter and amplifier units were provided by Proplus 9812B. In order to apply repetitive SC stress on the DUT, a circuit shown in Fig. 2 was set up. Repetitive SC tests was performed under the ${V} _{\mathrm{ gs}}$ of 19/−4 V and ${V} _{\mathrm{ ds}}$ of 250 V. The gate pulse width (${T} _{\mathrm{ sc}}$ ) of $20~\mu \text{s}$ and the interval time of 3 s between repetitive SC cycles were chosen to avoid overheating the device. The SC currents under different ${T} _{\mathrm{ sc}}$ were captured by an oscilloscope (Tektronix DPO 5034) as shown in Fig. 3. At the beginning of the gate pulse, ${I} _{\mathrm{ ds}}$ rise rapidly to a peak value of 294 A. Then it keeps decreasing during the stress time due to the increase of junction temperature, and it is in agreement with previous result [24].

FIGURE 1.

Device structure: (a) the schematic diagram of cross section and (b) photograph of 1.2-kV/30-A SiC power MOSFETs.

FIGURE 2.

Schematic diagram of the test circuit.

FIGURE 3.

Current waveforms of the SiC power MOSFETs during the SC stress under the conditions of ${V} _{\mathrm{ gs}} =$ 19 V and ${V} _{\mathrm{ DD}} =$ 250 V.

SECTION III. Results and Discussion

A. Effect of Repetitive SC Stress on Electrical Characteristics

To explore the effect of repetitive SC stress on the electrical properties of SiC power MOSFETs, the output characteristics and the transfer characteristics were measured for the fresh devices and the ones after 1000 cycles of repetitive SC stress. the output characteristics of the DUT are plotted in Fig. 4, as for the SiC power MOSFETs after SC stress, the I_ds values obviously decrease with the increase of SC cycles at the same V_gs. Under the conditions of ${V} _{\mathrm{ gs}}=11$ V and ${V} _{\mathrm{ ds}}=5\text{V}$ , the typical I_ds value decrease from 26.76 A to 22.64 A after 500 SC cycles. Moreover, under the same conditions, the typical I_ds value decrease from 26.76 A to 16.51 A after 1000 SC cycles. The transfer characteristics are shown in Fig. 5, the transfer characteristics curves shift positively with the increase of SC cycles.

FIGURE 4.

Output characteristics of 1.2-kV 30-A SiC power MOSFETs with the increase of SC cycles at ${V} _{\mathrm{ gs}} =7$ , 9, 11, 13 and 15 V.

FIGURE 5.

Transfer characteristics of 1.2-kV 30-A SiC power MOSFETs with the increase of SC cycles at ${V} _{\mathrm{ ds}} =20$ V.

Fig. 6 shows the SC cycles-dependent ${R} _{\mathrm{ dson}}$ and ${V} _{\mathrm{ th}}$ of SiC power MOSFETs. The values of the ${R} _{\mathrm{ dson}}$ and ${V} _{\mathrm{ th}}$ increase with SC cycles. Under the conditions of ${V} _{\mathrm{ ds}}=V_{\mathrm{ gs}}$ and ${I} _{\mathrm{ ds}}=1$ mA, the typical ${V} _{\mathrm{ th}}$ value increase from 3.14 V to 3.62 V after 500 SC cycles. Under the conditions of ${V} _{\mathrm{ gs}}=20$ V and ${I} _{\mathrm{ ds}}=20$ A, the typical ${R} _{\mathrm{ dson}}$ value increase from 91.34 $\text{m}\Omega$ to 113.55 $\text{m}\Omega$ after 1000 SC cycles. It indicates that the effect of SC stress on the device is notable, and the results are in agreement with previous results [8]. The total ${R} _{\mathrm{ dson}}$ of power MOSFETs is composed of two parts: the channel resistance (${R} _{\mathrm{ ch}}$ ), and the residual resistance (${R} _{\mathrm{ s}}$ ). The ${R} _{\mathrm{ s}}$ of power MOSFETs can be obtained from the dependence of ${R} _{\mathrm{ dson}}$ on (${V} _{\mathrm{ g}}-{V}_{\mathrm{ th}}$ )⁻¹ [25]. Taking the additional account of ${R} _{\mathrm{ s}}$ , the entire ${R} _{\mathrm{ dson}}$ of power MOSFETs can be expressed as:

$$\begin{equation*} {R}_{dson} {=}\frac {L}{\mu _{n}{C}_{ox}{W}} \times \frac {1}{V_{g}-{V}_{th}} {+R}_{s}\tag{1}\end{equation*}$$ where ${L}$ is the gate length, ${C} _{\mathrm{ ox}}$ is the gate oxide capacitance, W is the gate width, and $\mu _{\mathrm{ n}}$ is the electron mobility. With the ${V} _{\mathrm{ th}}$ increase the ${R} _{\mathrm{ dson}}$ expressed positive correlation with the (${V} _{\mathrm{ g}}$ -${V} _{\mathrm{ th}}$ )⁻¹. The increase of ${R} _{\mathrm{ dson}}$ indicated degradation seems to be associated with the channel region, and continuous stressing leads to an overall increase in device ${R} _{\mathrm{ dson}}$ , aluminum reconstruction and cavities at the contact interface between the aluminum surface metallization and source contacts maybe occurred during SC stress due to junction temperature increases [11].

FIGURE 6.

${V} _{\mathrm{ th}}$ variation and ${R} _{\mathrm{ dson}}$ during the SC stress for a 1.2-kV 30-A SiC power MOSFETs.

Meanwhile, to explore the effect of repetitive SC stress on the gate oxide and the body diode, ${I} _{\mathrm{ gss}}$ and the blocking characteristics of the device were also monitored and shown in Fig. 7 and Fig. 8. After 500 SC cycles, the ${I} _{\mathrm{ gss}}$ and blocking characteristics remain good stability, while they greatly degrade after 1000 SC cycles of SC stress. The leakage current increases by orders of magnitude compare with the fresh DUT, which indicates that the gate oxide and the body diode suffer from catastrophic damage.

FIGURE 7.

${I} _{\mathrm{ gs}}$ -${V} _{gs }$ characteristics of 1.2-kV 19-A SiC power MOSFETs with the increase of SC cycles.

FIGURE 8.

Blocking characteristics of the SiC power MOSFETs after SC stress.

In order to trace the damage position, the ${C} _{\mathrm{ g}}$ –${V} _{\mathrm{ g}}$ characteristics of the device after different SC stress cycles are shown in Fig. 9 (due to the ${I} _{\mathrm{ gss}}$ increases greatly by orders of magnitude the ${C} _{\mathrm{ g}}$ –${V} _{\mathrm{ g}}$ characteristics of the devicesafter 1000 SC cycles of SC stress cannot be measured). During the measurement, the gate was biased at a certain voltage while drain and source of the device are grounded. A 25 mV small AC voltage (${V} _{ac}$ ) signal with 1 MHz frequency was added to the gate to detect ${C} _{\mathrm{ g}}$ . The ${C} _{\mathrm{ g}}$ –${V} _{\mathrm{ g}}$ curves of the device could be divided into five parts based on the value of ${V} _{\mathrm{ g}}$ . When the gate is strong positively biased, the channel is inversed and the JFET region is accumulated. With the decrease of V_g, the channel turns out to deplete. Then the JFET region starts to deplete, when the channel is accumulated, the capacitance reaches the lowest value. Until the JFET region gets inversed, the whole capacitance increases again. The Five different surface situations of accumulation and depletion of JFET region and channel region are correspond to the five parts in Fig. 9. The C_g in part I, II, III and IV can respectively be expressed as [26]:

$$\begin{equation*} C_{g} =C_{oc} +C_{oj} =C_{ox}\tag{2}\end{equation*}$$ where ${C} _{\mathrm{ oc}}$ and ${C} _{\mathrm{ oj}}$ represent for the oxide capacitances of the channel region and the JFET region, respectively. $$\begin{align*} C_{g}=&\frac {1}{\frac {1}{C_{oc} } +\frac {1}{C_{dc} } } +C_{oj}\tag{3}\\ C_{g}=&\frac {1}{\frac {1}{C_{oc} } +\frac {1}{C_{dc} } } +\frac {1}{\frac {1}{C_{oj} } +\frac { 1}{C_{dj} } }\tag{4}\\ C_{g}=&C_{oc} +\frac {1}{\frac {1}{C_{oj} } +\frac {1}{C_{dj} } }\tag{5}\end{align*}$$ where ${C} _{\mathrm{ dc}}$ is the depletion capacitance of the channel region and ${C} _{dj}$ is the depletion capacitance of the JFET region.

FIGURE 9.

Variations of the ${C} _{\mathrm{ g}}$ -${V} _{\mathrm{ g}}$ characteristic of the device under different SC cycles.

By the shifts of part I to part V in ${C} _{\mathrm{ g}}$ –${V} _{\mathrm{ g}}$ curve, the damage position and the types of the charges injected into the gate oxide can be obtained. From Fig. 9, there is obvious positive-shift on the part II while there is slight positive-shift on part III and part IV. This illustrates that during the repetitive SC cycles negative charges were injected into the gate oxide under channel region. However, the JFET region was slightly affected by stress. The results are consistent with the previous works [8].

B. Effect of Repetitive SC Stress on Low Frequency Noise

From the ${C} _{\mathrm{ g}}$ –${V} _{\mathrm{ g}}$ results mentioned above, the generated traps are mainly located in the gate oxide under channel region. LFN measurements are presented to be a valid method to characterization the defects and the density of interface states in channel region of semiconductor device. The spectral noise power density of the SiC power MOSFETs can be calculated based on the LFN results. According to the theory of 1/ f noise, the 1/${f}$ noise is caused by random capture/release of carriers by defects at the SiC/SiO2 interface. Therefore, according to the LFN characteristics before and after the SC stress of the device, the change in the density of defect states can be determined. To further explore the effect of SC stress on the defect in SiC power MOSFETs, the LFN power spectrum was measured under different gate bias voltages, and the current spectral noise density ($S_{I}$ ) was measured at low drain bias ($V_{\mathrm{ ds}}=$ 100 mV) as shown in Fig. 10. The normalized $S_{I}$ / I² is 1/f with the frequency in the range of 1 Hz to 100 Hz for the typical SiC power MOSFETs as shown in Fig. 10 (a). The normalized current spectral density $S_{I}$ / I² taken at 10 Hz is plotted in Figs. 10 (b)-(d) versus the current of the fresh device, 200 and 500 SC cycles device, respectively. The number fluctuation model explains the 1/ f noise by the charge trapping/detrapping of mobile carriers between interfacial traps and the channel, and the $S_{I}$ / I² can be modeled by [27]:

$$\begin{equation*} {S_{I} \mathord {\left /{ {\vphantom {S_{I} I_{_{} }^{2} }} }\right. } I_{_{} }^{2} } =({g_{m} \mathord {\left /{ {\vphantom {g_{m} I_{} }} }\right. } I_{} })^{2} S_{vf{b}}\tag{6}\end{equation*}$$ where $S_{vbf}$ as input-referred spectral noise density was adjusted here to achieve a good fit to the data, and $g_{m}$ /I_d extracted from the measured characteristics. The $S_{vfb}$ are $2.1\times 10^{-1}{}^{2}$ , $4.5\times 10^{-1}{}^{2}$ and $7.5\times 10^{-1}{}^{2}$ (V²/Hz) for the fresh device, 200 and 500 SC cycles device, respectively. Then, it was possible to determine the density of traps ($N_{it}$ ) by: $$\begin{equation*} S_{vf{b}} ={q^{2} kT\lambda N_{it} \mathord {\left /{ {\vphantom {q^{2} kT\lambda N_{it} WLfC_{ox}^{2} }} }\right. } WLfC_{ox}^{2} }\tag{7}\end{equation*}$$ where $\lambda$ is the tunneling attenuation coefficient (0.1 nm for SiO2), ${W}$ and ${L}$ are the gate width and length, respectively, and C_ox is the capacitance of SiO₂ per unit area. From the equation, as a first order estimate, the extracted $N_{it}$ are $3.87\times 10^{1}{}^{7}$ , $8.28\times 10^{1}{}^{7}$ and $1.38\times 10^{1}{}^{8 }$ cm⁻³eV⁻¹ for the fresh device, 200 and 500 SC cycles device, respectively.

FIGURE 10.

The characteristics of low frequency noise for SiC power MOSFETs: (a) the typical $S_{I}$ / I² versus frequency for the fresh devices, and (b)-(d) the $S_{I}$ / I² at 10 Hz versus ${I} _{\mathrm{ ds}}$ for the fresh device, 200 and 500 SC cycles device, respectively.

C. Mechanism of SC Stress on SiC MOSFETs

To explain the degradation mechanism, the schematic diagram of the physical mechanism is shown in Fig. 11. The fresh device schematic diagram and energy band diagram are shown in Fig. 11 (a). At the near-interfacial SiC/SiO₂ of the fresh SiC power MOSFETs, defects generally can be grouped into three kinds: bulk oxide traps, interface traps, and border traps [14]. Carbon vacancy clusters in the near-interfacial SiO₂/SiC (interface traps) are the most common defect responsible for 1/${f}$ noise [28], they are located at shallow levels [29], and it is often believed that the SiC/SiO2 interface contains excess carbaon [30], [31]. Furthermore, the incompletely ionized N dopants from postoxidation NO processing could also result in fluctuations in carrier number [32], [33]. Therefore, these traps of the fresh devices could be detected by the LFN method as shown in Fig. 10 (b).

FIGURE 11.

Schematic diagram of the physical mechanism for the effect of SC stress on SiC power MOSFETs: (a) traps at the SiC/SiO₂ of channel for the fresh device, (b) more traps for the device after the SC stress, (c) and (d) are corresponding to the energy band diagram of the device before and after SC stress, respectively.

schematic diagram and energy band diagram of the SC degraded devices are shown in Fig. 11 (b). As for the SiC power MOSFETs during SC stress, the channel region is suffered from a peak ionization rate and perpendicular electrical field [34]. Meanwhile, high temperature also accumulation at the SiC/SiO₂ interface of the SiC power MOSFETs [35]. During SC stress, the bond of Si-C could be broken, and addition carbon vacancies could be generated. Furthermore, the Si=N bonds also broken. Thus, active traps would be formed. The results in the increase of defect, which is supported by the extracted $N_{it}$ results as shown in Fig. 10(b)-(d). Moreover, the negative charges tunnel directly into the intrinsic and the near-interfacial oxide traps could be activated [36], [37], and this leads to the ${I} _{\mathrm{ ds}}$ decrease and positive shift of ${V} _{\mathrm{ th}}$ as shown in Fig. 4 and Fig. 6.

SECTION IV. Conclusion

The degradation behavior and mechanisms of SiC power MOSFETs under repetitive SC stress were investigated. The repetitive SC stress leads to the degradation of the devices, such as the significantly increase of the ${R} _{\mathrm{ on}}$ and ${V} _{\mathrm{ th}}$ . Besides, the ${I} _{\mathrm{ gss}}$ increase greatly and blocking characteristics of the SiC power MOSFET were deteriorated after 1000 cycles of SC stress. Moreover, ${C} _{\mathrm{ g}}$ -${V} _{\mathrm{ g}}$ curves and LFN characteristics before and after SC stress were measured. The damage region was confirmed on channel region along the SiC/SiO₂ interface by the positive shift of ${C} _{\mathrm{ g}}$ -${V} _{\mathrm{ g}}$ curves. Based on the LFN results, the trap density of SiC/SiO₂ interface and oxide layer gradually increase after repetitive SC stress. Due to the peak ionization rate, the perpendicular electrical field and high temperature on the channel region of gate oxide during SC stress, the physical mechanism could be attributed to electrically active traps generated at SiC/SiO₂ interface and in the oxide layer. The results of this study may be useful to provide reference for converters design and fault protection of SiC power MOSFETs.