A Ka-Band Scalable Hybrid Phased Array Based on Four-Element ICs

In this article, a scalable hybrid phased-array system is presented through synchronization, analog complex weighting, and digital beamforming of numerous fully integrated Ka-band four-receiver (RX)/four-transmitter (TX) phased-array transceiver integrated circuits (ICs). A 1.09-GHz clock synchronizes the local oscillator (LO) and a 50-MHz clock synchronizes analog-to-digital (A/D)/digital-to-analog (D/A) converters for all array elements. Phase shifting is first accomplished in the analog domain using optimal intermediate frequency (IF)/LO complex weighting and signal summing in the 4RX/4TX IC to reduce the number of signals by a factor of four, followed by A/D sampling and digital beamforming in field-programmable gate arrays (FPGAs) and central processing units (CPUs). Phase-shifting properties, programmable gain variations, and antenna patterns of each RTX channel are measured and tabulated to calculate the optimal channel weights. The long-term phase stability is enhanced through temperature control by monitoring all ICs' temperatures in real time and adaptively adjusting the duty cycle of the TX mode of each IC to limit instantaneous temperature variations to ±0.5 °C over each calibration session. This reduces random phase errors from 13.3° to 4.8° in the TX mode. After each Vivaldi antenna is located on a 2-D rectangular grid, an 8×4 subarray module with synchronized digital output is demonstrated. With the boresight pointing along the x̂-axis, the eight-element dimension pointing along the ŷ-axis, and the four-element dimension pointing along the ẑ-axis, this subarray steers radiation patterns with the E⃗ -field polarized to the ŷ-axis between ±40° in both azimuth and elevation with 13.4° and 26.4° measured 3-dB beamwidths, respectively.

I. Introduction

The -element phased-array transceivers’ transmitting equivalent isotropic radiated power (EIRP) increases proportionally to , and the receiving signal-to-noise ratio (SNR) improves linearly with . Because of advances in process technologies and reductions in process variations at a specific performance, the number () of array elements integrated on a single die or a single wafer has increased over the decade. Particularly at millimeter-wave frequencies, 32- to 256-element integrated circuits (ICs) [1]–[3] have been reported. Integrating a large number of phased-array elements reduces system-level complexity and variation by integrating all inter-element radio-frequency (RF) and local oscillator (LO) routings on the chip, leaving only the antenna ports and array I/Os that will be routed off-the-chip to the antennas and back-end transceiver, respectively. This facilitates system engineers to easily apply the chips for multiple-input multiple-output (MIMO) communication [4], [5] and reduces the overall cost per array element [6]–[9].