I. Introduction
The VOLTAGE source inverters (VSIs) are widely used in many power conversion applications and are often connected in parallel to achieve the higher output current, effectively increasing the power rating [1], [2]. The paralleled inverters are highly modular and eligible for the utilization of fault-tolerant techniques, ensuring the system reliability [3]. In a paralleled system, one of the important concerns is the circulating current. When VSIs are connected in parallel with the common dc and ac buses, the circulating current is introduced because of the instantaneous voltage difference of the paralleled-legs, which is often caused by the imperfect symmetry in hardware or control of paralleled inverters [4]. In addition, the paralleled inverters operated with interleaved pulsewidth modulation (PWM) have been increasingly attractive due to its capability of line current harmonics reduction and passive component reduction. With the interleaving operation, the circulating current can be enlarged because of the voltage difference introduced intentionally [5], [6]. Since the circulating current may bring the higher power loss, overstress the power devices, and saturate the inductors, its critical issue must be solved [7], [8].