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Variable Switching Frequency PWM Strategy for High-Frequency Circulating Current Control in Paralleled Inverters With Coupled Inductors | IEEE Journals & Magazine | IEEE Xplore

Variable Switching Frequency PWM Strategy for High-Frequency Circulating Current Control in Paralleled Inverters With Coupled Inductors


Abstract:

Determination of high-frequency circulating current is important for coupled inductor design of paralleled voltage source inverters (VSIs). A time-domain model describing...Show More

Abstract:

Determination of high-frequency circulating current is important for coupled inductor design of paralleled voltage source inverters (VSIs). A time-domain model describing the circulating current of coupled inductor within a switching period is presented in this article. Using this model, the peak or rms values of circulating current can be calculated for different pulsewidth modulation (PWM) methods. Both the conventional 180° interleaved PWM and zero-common-mode voltage PWM algorithms are studied here. Considering the saturation nature of the magnetic cores in determining the effective inductance of coupled inductors, the variable switching frequency PWM (VSFPWM) is proposed to better utilize the coupled inductor's saturation limit, which is determined by high-frequency circulating current peak value. With the proposed strategy, both switching losses and electromagnetic interference are improved with respect to the constant switching frequency PWM. Moreover, the detailed power losses analysis of paralleled VSIs has been presented and the dynamic performance of the proposed VSFPWM has been well investigated. Finally, the proposed method has been extended to the system with 2N paralleled inverters. Detailed simulation and experimental results are provided to validate the proposed method.
Published in: IEEE Transactions on Power Electronics ( Volume: 35, Issue: 5, May 2020)
Page(s): 5366 - 5380
Date of Publication: 20 September 2019

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I. Introduction

The VOLTAGE source inverters (VSIs) are widely used in many power conversion applications and are often connected in parallel to achieve the higher output current, effectively increasing the power rating [1], [2]. The paralleled inverters are highly modular and eligible for the utilization of fault-tolerant techniques, ensuring the system reliability [3]. In a paralleled system, one of the important concerns is the circulating current. When VSIs are connected in parallel with the common dc and ac buses, the circulating current is introduced because of the instantaneous voltage difference of the paralleled-legs, which is often caused by the imperfect symmetry in hardware or control of paralleled inverters [4]. In addition, the paralleled inverters operated with interleaved pulsewidth modulation (PWM) have been increasingly attractive due to its capability of line current harmonics reduction and passive component reduction. With the interleaving operation, the circulating current can be enlarged because of the voltage difference introduced intentionally [5], [6]. Since the circulating current may bring the higher power loss, overstress the power devices, and saturate the inductors, its critical issue must be solved [7], [8].

References

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