Mapping and scheduling techniques in NoC: A survey of the state of the art

Mapping and Scheduling techniques represent critical steps on assigning application tasks and ordering the communication between those tasks on Network on Chip (NoC) architecture in order to enhance and optimize some predefined metrics or performances of the NoC architecture. However, the aim of this paper is to present a detailed state of the art of realized researches on the last two decades in the field of optimization of both mapping and scheduling of applications onto Network on Chip architectures, also a classification of static mapping and dynamic mapping onto NoC were presented.

I. Introduction

Now a day, the huge demands of powerful and scalable systems that support large number of communications, multiprocessor System on Chip (MPSoC) are no more suitable to support these huge demands, since they incrementally produce gaps and complexity in both designing and communications [1]. For that, Network on Chip (NoC) is an alternative interconnect solution which is considered as a new promising design in terms of ending the productivity issues and offering an infrastructure communication to overcome the use of MPSoC that stand for using bus methodology [2]. NoC architecture consists of many heterogeneous intellectual property (IP) cores and links between them using network as support of communication, where several routers and switches are integrated in each node for parallel transferring of flits (the flits are the transfer unit in NoC).