Design of a Low-Voltage CMOS Mixer with Improved Linearity

This paper presents a low-voltage CMOS (complementary-metal-oxide-semiconductor) mixer with low power consumption. By using the folded-cascade structure, the problem on high supply voltage of the stacking transconductance-stage and switching-stage is solved. Firstly, a differential cross-coupling structure is used to improve transconductance-stage's linearity without decreasing voltage margin. Then, two inductors are used as the RF (Radio Frequency) choke, which could prevent the leakage of the input RF signal at design frequency without consuming direct-current voltage. Finally, the low-voltage CMOS folded-cascade mixer is designed and verified on a TSMC 0.18 um RF CMOS process. The simulation results show that the mixer features a conversion gain of 15.8 dB, a noise figure of 11 dB, a third-order input intercept point (IIP3) of 1.4 dBm, and consumes only 3 mW at a power supply voltage of 1.2 V.

I. Introduction

As the CMOS process technology developing to the deep submicron/nanometer, the power supply voltage is getting lower and lower, which reduces the power consumption of the system and improves the density of the system integration. Low voltage and low power consumption have become the main development direction of the CMOS integrated circuit industry [ 1 – 3 ]. In addition, with reducing of the process dimension, the MOSFET’s cut-off frequency is increasing, which makes the CMOS technology gradually moving towards to RF and millimeter-wave application, and its market share is increasing year by year.