A Low Power Sub-harmonic Self-Oscillating Mixer with 16.8dB conversion loss at 310GHz in 65nm CMOS

A 310GHz sub-harmonic self-oscillating mixer (SHSOM) with on-chip LO generation is demonstrated in this paper. The mixer consists of four Clapp oscillators that are differentially coupled to the adjacent one. Two patch antennas deliver the differential RF signal to the mixer/oscillator and with the large LO swings at the transistor terminals, high conversion gain is achieved. By controlling the phase shift of the RF signal between gate and drain, the conversion gain is boosted. Using a 65nm CMOS technology, the prototype of the SHSOM achieves 16.8 dB conversion loss and 21.3 dB noise Figure at 310GHz. The 3-dB IF bandwidth is more than 8GHz and DC power consumption is around 55mW in total.

I. Introduction

Wireless terahertz applications including spectroscopy, high data-rate communication, high resolution radar and imaging system demand receivers with decent noise Figure performance. However, insufficient f_max of the transistors makes it challenging to implement suitable LNA for a terahertz receiver in a silicon process. As a result, mixer-first or envelope detector-first topologies are generally adopted [1]–[7]. Mixers can maintain the phase information of the signal and therefore can be used in coherent receivers. Conversion gain of a mixer is proportional to the LO power before it gets saturated [4]. Therefore, to achieve acceptable conversion gain and noise Figure performance in mm-wave and THz mixers, off-chip LO with on-chip multiplier/amplifier chain is usually adopted to provide strong LO swing with good phase noise performance. However, on-chip multiplier/amplifier chain occupies considerable area and degrades the integration level. Besides, the DC power consumption is significantly increased.