An SEU/SET-Tolerant Phase Frequency Detector With Double-Loop Self-Sampling Technology for Clock Data Recovery

A hardened phase frequency detector (PFD) employing double-loop self-sampling technology is proposed for clock and data recovery. The PFD can remove the error state and maintain the correct state by the use of the sampler. The laser experiment shows that the threshold value of the proposed PFD has been greatly improved.

I. Introduction

To improve the data rate of the chip-to-chip interconnects, the serializer and deserializer (SerDes) system should be used. Clock and data recovery (CDR) is a critical block in SerDes [1]–[3]. A phase-locked loop (PLL) can be used to recover the clock and data. It has been considered as a sensitive point in space-deployed electronics [4]–[6]. Any disturbance in the output clock phase may increase the bit error rate (BER). From a design point of view, the BER of SerDes should be as small as possible to meet the receiver interference tolerance test requirements of section 85.8.4.2 in the IEEE Standard 802.3, generally not exceeding 10⁻¹² in the normal state.