A W-Band SiGe Transceiver with Built-in Self-Test

A fully integrated W-band silicon-germanium (SiGe) transceiver is presented which provides a loop-back built-in self-test (BIST) functionality that allows continuous monitoring of the health of the system while in use. In addition, it facilitates on-die measurement of the transmit and receive channels to aid in characterization of the transceivers inside a large phased array system. Measurement results show a close agreement between the on-die and off-chip characterization results. The transceiver can switch from normal operation mode to BIST mode by applying a control signal. Measurement shows receiver SSB noise figure of 12 dB and P1dB of -8.5 dBm and transmitter output power of +8 dBm. The power consumption of the entire transceiver is 150 mW.

I. Introduction

SiGe and CMOS technologies offer better reliability and yield, on larger wafers compared to their III-V counterparts, resulting in lower cost and much higher integration levels, which allows the implementation of large millimetre-wave (mmW) phased array systems in these types of technologies. However, the characterization of mmW systems, especially large phased arrays, is very costly and time consuming. In addition, there is a high demand for an on-die monitoring system to continuously verify the functionality of the system health while in a fielded environment. This is very important, especially for extreme environment applications such as space [1], and for those applications that can jeopardise human lives upon the failure of electronic systems, such as for automotive radars [2]. For these reasons, an accurate ondie monitoring system is highly desirable. A number of approaches have recently been developed to provide on-die built-in self-test (BIST) functionality at mmW. In the BIST mode, a test signal is required to feed into the system, and a mechanism is also required to measure the signal levels accurately at various nodes, all without affecting the system performance. In [3], on-chip test sources were implemented to provide RF test signals for characterization, which may limit the bandwidth of the BIST system. In [4], a portion of the LO signal was distributed across the chip to provide an RF test signal for the phased array elements. This technique requires extra dc consumption for the LO distribution network and the receiver must be dc-coupled to produce an IF signal at the output. In [5], on-chip IF signal generation circuitry, including on-die direct digital synthesizer (DDS), was utilized to provide an RF test signal by mixing with the available LO signal on the chip. In [6], front-end single-pole single throw switch (SPST) with a shunt attenuation path was utilized for a simple realization of the loop-back BIST circuit. Although the utilized configuration is simple and compact, the reflective characteristics of the switches in BIST mode, may damage the high-power PA or result in inaccurate characterization of the PA in BIST mode.