Abstract:
A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used ...Show MoreMetadata
Abstract:
A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique is applied to extract the intrinsic gate capacitance. Applicability of the method is demonstrated for ultra-thin nitride/oxide (N/O /spl sim/1.4 nm/0.7 nm) composite dielectric MOSFETs.
Published in: IEEE Transactions on Electron Devices ( Volume: 47, Issue: 10, October 2000)
DOI: 10.1109/16.870559
References is not available for this document.
Select All
1.
E. J. Lerner, "The end of the road for Moores law", IBM J. Res. Develop., pp. 6-11, 1999.
2.
K. J. Yang and C. Hu, "MOS capacitance measurements for high-leakage thin dielectrics", IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, July 1999.
3.
C.-H. Choi, " MOS \$C-V\$ characterization of ultra-thin gate oxide thickness (1.3.8 nm) ", IEEE Electron Device Lett., vol. 20, pp. 292-294, June 1999.
4.
K. Ahmed, "Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-Å gate oxide MOSFETs", IEEE Trans. Electron Devices, vol. 46, pp. 1650-1655, Aug. 1999.
5.
E. M. Vogel, W. K. Henson, C. A. Richter and J. S. Suehle, "Limitations of Conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics", IEEE Trans. Electron Devices, vol. 47, pp. 601-608, Mar. 2000.
6.
W. K. Henson, "Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors", IEEE Electron Device Lett., vol. 20, pp. 179-181, Apr. 1999.
7.
S. H. Lo, " Modeling and characterization of n \$^{+}\$ and p \$^{+}\$ polysilicon-gated ultra thin oxides (21 Å) ", Proc. Symp. VLSI Technol., pp. 149-150, 1997.
8.
N. D. Arora, MOSFET Model for VLSI Circuit Simulation, Germany, Berlin:Springer-Verlag, 1993.
9.
M. J. van Dort, P. H. Woerlee and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFETs at inversion conditions", Solid-State Electron., vol. 37, pp. 411, 1994.
10.
W. Hänsch (Hamsch), T. Vogelsang, R. Kircher and M. Orlowski, " Carrier transport near the Si/SiO \$_2\$ interface of a MOSFET ", Solid-State Electron., vol. 32, pp. 839, 1989.
11.
P. Vande Voorde, "Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETs", IEDM Tech. Dig., pp. 811, 1996.
12.
C. Bowen, "Physical oxide thickness extraction and verification using quantum mechanical simulation", IEDM Tech. Dig., pp. 869-872, 1997.
13.
S. Nagano, M. Tsukiji, E. Hasegawa and A. Ishitani, " Mechanism of leakage current through the nano-scale SiO \$_{2}\$ layer ", J. Appl. Phys., vol. 75, pp. 3530, 1994.
14.
C. S. Rafferty, "Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques", Proc. Conf. Simulation Semiconductor Processes and Devices, pp. 137-140, 1999.
15.
H. S. Momose, "1.5 nm direct-tunneling gate oxide Si MOSFETs", IEEE Trans. Electron Devices, vol. 43, pp. 1233-1242, Aug. 1996.
16.
C.-H. Choi, "\$C-V\$ and gate tunneling current characterization of ultra-thin gate oxide MOS ( \$t_{ox}=1.3\$ .8 nm) ", Proc. Symp. VLSI Technol., pp. 151-152, 1999.
17.
H. S. Momose, " A study of flicker noise in N \$^{-}\$ and P \$^{-}\$ MOSFETs with ultra-thin gate oxide in the direct-tunneling regime ", IEDM Tech. Dig., pp. 923-926, 1998.
18.
Y. Wu and G. Lucovsky, " Ultrathin nitride/oxide (N/O) gate dielectrics for p \$^{+}\$ -polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced CVD/thermal oxidation process ", IEEE Electron Device Lett., vol. 19, pp. 367-369, Oct. 1998.
19.
Y. Wu, Y.-M. Lee and G. Lucovsky, "1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process", IEEE Electron Device Lett., vol. 21, pp. 116-118, Mar. 2000.
20.
K. Kano, Semiconductor Devices, NJ, Englewood Cliffs:Prentice-Hall, 1998.
21.
Y. Taur and T. Ning, Fundamental of Modern VLSI Device, U.K., Cambridge:Cambridge Univ. Press, 1998.
22.
HSPICE Users Manual, AVANT! Corp., 1998.
23.
K. Doganis and D. L. Scharfetter, "General optimization and extraction of IC device model parameters", IEEE Trans. Computer-Aided Design, vol. 30, pp. 1219-1228, Sept. 1983.