Contents I. Introduction
Interest in the next generation of integrated circuits has focused on devices having higher levels of integration, larger area, and greater flexibility. Recent research on vertical-stacked logic circuits using thin-film transistors (TFTs) has attracted attention because the resulting stack covers a small area and yet remains thin [1], [2]. Thus, the 3-D multilayer stack structure is one road to the next generation of integrated circuits. Among its variations, amorphous oxide semiconductor TFTs (AOS TFTs) are attracting attention as they avoid some problems arising with conventional amorphous silicon (a-Si). Among them, amorphous indium–gallium–zinc–oxide (a-IGZO) is the most representative AOS material [3], [4]. However, indium and gallium are very expensive materials due to the rare metals on earth, so indium-free materials as a-Si–zinc–tin–oxide (a-SZTO) have been extensively studied to replace a-IGZO. a-SZTO demonstrates favorable electrical properties such as high mobility (>15 cm) and wide ON/OFF current ratio (>108) and high stability comparable with a-IGZO [5]–[7]. Complementary metal–oxide–semiconductors (CMOS), consisting essentially of n- and p-type materials in combination, have been studied extensively [8]. The CMOS structure is well known as an essential element for circuit construction because it shows several advantages as follows: 1) the CMOS plays an essential role in implementing low-power devices in a circuit. The reason for this is that the pMOS is driven only in the standby state, and the nMOS is driven only when it is in the operate state and 2) in addition, the voltage gain of the NOT circuit is high. This is because the p-type subthreshold slope (SS) can also be affected. In the case of the only n-type circuit, it is difficult to secure the high-voltage gain because it is strongly dependent on the SS value of the E-mode. However, p-type oxide semiconductors have lower electrical characteristics (than, e.g., mobility, ON/OFF current ratio) producing instability in devices and making CMOS implementation difficult. In other words, due to the intrinsic nature of oxide semiconductors, oxygen vacancies are accepted as the main mechanism for electron generation [9], [10]. For this reason, it is very difficult to substantiate the p-type characteristics. Recently, Lee et al. [11] and Jeong et al. [12] studied electrical properties under light illumination stress and noise characteristics, in p-type SnO [11], [12]. Despite this continued research, there is still a lack of understanding of p-type characteristics in oxide semiconductors. To address this problem, CMOS devices having hybrid structures have been fabricated, with the n-type characteristics derived from an oxide semiconductor and the p-type from carbon nanotubes [13] or organic TFTs [14]. However, having such a hybrid structure for CMOSs increases the number of process steps, is more complex, and becomes expensive. In comparison, a logic circuit using only an n-type TFT as the basic structure can be fabricated through a simple process using an oxide semiconductor. When such a structure is used, the threshold voltage () is adjusted to constitute a depletion-mode or an enhancement-mode type device, to constitute an inverter or logic circuit, respectively. Conventionally, adjusting by means of a channel layer has been used, such as by controlling doping in the channel layer [15], changing the layer thickness [16], and using stacked structures [17]. Research on logic circuits according to their channel layer structure has been ongoing; however, the effect of factors such as electrode materials and gate insulators is still much less understood.
