Analysis of Press-Pack SiC MOEFET’S Parasitic Resistance

To press-pack devices, higher packaging resistance results in higher conduction losses. In this paper, compositions of the packing resistance are studied for a press-pack SiC MOSFET. Firstly an estimation method of body resistance of conducting layers in the press-pack SiC MOSFET with ANSYS Q3D is investigated, which is verified by the experiment. Since the Q3D resistance estimation method is unable to obtain contact resistances between different layers in the press-pack, the contact resistances estimation method is proposed. Finally all resistances in the press-pack are obtained. It is concluded that the contact resistance is critical to the static loss of the press-pack. It is useful to the press-pack structure improvement in the future.

I. Introduction

With the development of power electronics technology, the application of high-power device is growing rapidly such as HVDC transmission systems, locomotive tractions and so on. Silicon carbide (SiC) devices has the advantages in high frequency, high voltage and high temperature operations. As the traditional silicon (Si) device counterpart, SiC module suffers from wire bond. For higher reliability applications such as HVDC, high-speed train traction etc, press-pack SiC MOSFET is needed. Press-pack IGBT has been commercialized and many of R&D works have been carried. In [1] , the press-pack IGBT use Nanosilver paste as a die attachment material for 3300V power chips to eliminate the pressure contact. In [2] , the method of thermal structure function is proposed to measure the thermal contact resistance between multilayers within PP IGBTs. A platform to test dynamic switching performance for press-pack IGBT modules is designed and implemented by employing the principle of double-pulse test [3] . Press-pack IGBT modules have been used in 200MW MMC-HVDC [4] .