Analysis of Device Characteristics of Dual material Double gate Strained N-Channel MOSFET

With the objective to achieve high drain current at lesser dimension in CMOS technology, device dimension reaches to Sub Nm region and undesirable effect such as short channel effect, high leakage current, DIBL are get introduced. And the desired characteristics become disturbed. As a solution to these problems, we have proposed a structure of Double material Double Gate strained n- MOSFET in this paper. This has an ability to reduce hot carrier effect and DIBL and have high drain current also due to presence of strained channel. Simulation work has been done on ATLAS, a 2D device simulator from Silvaco Inc.

I. INTRODUCTION

As the device dimension reaches to Sub Nm region in CMOS technology, undesirable effect like short channel effect, large leakage current, DIBL starts plaguing and the device characteristics become disturbed. According to the law of scaling, in planar MOSFET for continuous scaling of channel length it is required to keep high doping in channel region. By this lower junction electric field is maintained inside the channel region. Also highly doped Source and Drain depletion regions does not overlap as high doping ensures reduction in depletion layer width. But increase in doping causes a degradation in mobility in channel region due to impurity scattering. So some significant change in device structures and material will be needed to improve the performance. Strained Si devices promises a solution for this problem because it gives enhancement in mobility and hence increase in drain current due to change in energy band structure of silicon under stress which gives better performance even at highly scaled channel length. When a silicon layer is grown on to a relaxed Si_1-x Ge_x then a biaxial strain is produced in the silicon epitaxial layer due to lattice mismatch between silicon and SiGe layer (due to larger lattice constant of Ge). [5] In silicon 6 degenerate energy lobes are present these are named as two perpendicular Δ₂ states and four Δ₄ states parallel to the plane. When a stress is applied to the Silicon layer these energy states are split into higher and lower energy states and this provide a lower energy states for electron to move and hence scattering of electron become less and mobility increases. Thus advantages achieved are modified lattice constant of the material and modified energy band structure to trap carriers through well formation and finally an enhanced mobility [2]. Now as concentration of Ge in Si_1-x Ge_x is increased amount of biaxial strain and mobility is increased further.