Enhanced IC Modeling Methodology for System-level ESD Simulation

To enable accurate system-level ESD simulation, the quasi-static I-V model of an IC is enhanced through kernel regression to reflect its circuit board dependency; alternatively, a recurrent neural network may be used to generate a non-quasi-static transient model. Hybrid electromagnetic and circuit simulation is demonstrated for ESD-induced noise coupling analysis.

I. Introduction

The Industry Council on ESD Target Levels advocates using SPICE-like circuit simulation to evaluate system-level ESD reliability, rather than first identifying problems at the time of product qualification testing [1]. This paradigm was named system efficient ESD design, or SEED. From the description of SEED provided in [1], circuit simulation is used to obtain the current and voltage waveforms at the “external pins” of any components that lie on the discharge path. One-port models that have been optimized for high-current ESD-like conditions are used to represent those external pins, and the reference terminal is connected to the system ground.